From e8614f71f88f292b8f8f6314880da692c5bbce9d Mon Sep 17 00:00:00 2001 From: Luke Kenneth Casson Leighton Date: Mon, 13 Dec 2021 14:16:00 +0000 Subject: [PATCH] add in missing MSRSpec import --- src/soc/experiment/test/test_ldst_pi_misalign.py | 1 + src/soc/experiment/test/test_loadstore1.py | 10 +++++----- 2 files changed, 6 insertions(+), 5 deletions(-) diff --git a/src/soc/experiment/test/test_ldst_pi_misalign.py b/src/soc/experiment/test/test_ldst_pi_misalign.py index c3faa85e..7b0fcd88 100644 --- a/src/soc/experiment/test/test_ldst_pi_misalign.py +++ b/src/soc/experiment/test/test_ldst_pi_misalign.py @@ -26,6 +26,7 @@ from soc.experiment.mmu import MMU from nmigen.compat.sim import run_simulation from openpower.test.wb_get import wb_get from openpower.test import wb_get as wbget +from openpower.decoder.power_enums import MSRSpec msr_default = MSRSpec(pr=1, dr=0, sf=1) # 64 bit by default diff --git a/src/soc/experiment/test/test_loadstore1.py b/src/soc/experiment/test/test_loadstore1.py index d6a7ae2b..293df275 100644 --- a/src/soc/experiment/test/test_loadstore1.py +++ b/src/soc/experiment/test/test_loadstore1.py @@ -816,8 +816,8 @@ def test_loadstore1_ifetch_multi(): if __name__ == '__main__': test_loadstore1() - test_loadstore1_invalid() - test_loadstore1_ifetch() - test_loadstore1_ifetch_invalid() - test_loadstore1_ifetch_multi() - test_loadstore1_ifetch_unit_iface() + #test_loadstore1_invalid() + #test_loadstore1_ifetch() + #test_loadstore1_ifetch_invalid() + #test_loadstore1_ifetch_multi() + #test_loadstore1_ifetch_unit_iface() -- 2.30.2