From e8719cfa2b198fee81336f723984d0ce540a5321 Mon Sep 17 00:00:00 2001 From: Luke Kenneth Casson Leighton Date: Tue, 7 Jul 2020 15:27:50 +0100 Subject: [PATCH 1/1] debugging termination / OP_ATTN --- src/soc/simple/core.py | 7 ++++--- src/soc/simple/test/test_core.py | 4 +++- src/soc/simple/test/test_issuer.py | 24 ++++++++++++++++-------- 3 files changed, 23 insertions(+), 12 deletions(-) diff --git a/src/soc/simple/core.py b/src/soc/simple/core.py index f2e1a1de..e8382f5d 100644 --- a/src/soc/simple/core.py +++ b/src/soc/simple/core.py @@ -32,6 +32,7 @@ from soc.decoder.power_decoder2 import PowerDecode2 from soc.decoder.decode2execute1 import Data from soc.experiment.l0_cache import TstL0CacheBuffer # test only from soc.config.test.test_loadstore import TestMemPspec +from soc.decoder.power_enums import InternalOp import operator @@ -98,9 +99,9 @@ class NonProductionCore(Elaboratable): # start/stop signalling with m.If(self.core_start_i): - m.d.sync += core_stopped.eq(1) - with m.If(self.core_stop_i): m.d.sync += core_stopped.eq(0) + with m.If(self.core_stop_i): + m.d.sync += core_stopped.eq(1) m.d.comb += self.core_terminated_o.eq(core_stopped) # connect up Function Units, then read/write ports @@ -134,7 +135,7 @@ class NonProductionCore(Elaboratable): # run this FunctionUnit if enabled, except if the instruction # is "attn" in which case we HALT. with m.If(enable): - with m.If(dec2.e.op.internal_op == InternalOp.OP_ATTN): + with m.If(dec2.e.do.insn_type == InternalOp.OP_ATTN): # check for ATTN: halt if true m.d.sync += core_stopped.eq(1) with m.Else(): diff --git a/src/soc/simple/test/test_core.py b/src/soc/simple/test/test_core.py index 578fa0ee..6e2ab94c 100644 --- a/src/soc/simple/test/test_core.py +++ b/src/soc/simple/test/test_core.py @@ -132,7 +132,9 @@ def check_regs(dut, sim, core, test, code): def wait_for_busy_hi(cu): while True: busy_o = yield cu.busy_o - if busy_o: + terminated_o = yield cu.core_terminated_o + if busy_o or terminated_o: + print("busy/terminated:", busy_o, terminated_o) break print("!busy",) yield diff --git a/src/soc/simple/test/test_issuer.py b/src/soc/simple/test/test_issuer.py index 1551ccfa..fd068a65 100644 --- a/src/soc/simple/test/test_issuer.py +++ b/src/soc/simple/test/test_issuer.py @@ -32,7 +32,7 @@ from soc.fu.cr.test.test_pipe_caller import CRTestCase from soc.fu.branch.test.test_pipe_caller import BranchTestCase from soc.fu.spr.test.test_pipe_caller import SPRTestCase from soc.fu.ldst.test.test_pipe_caller import LDSTTestCase -from soc.simulator.test_sim import GeneralTestCases +from soc.simulator.test_sim import (GeneralTestCases, AttnTestCase) def setup_i_memory(imem, startaddr, instructions): @@ -79,11 +79,6 @@ class TestRunner(FHDLTestCase): pdecode2 = core.pdecode2 l0 = core.l0 - # get core going - yield core.core_start_i.eq(1) - yield - yield core.core_start_i.eq(0) - comb += issuer.pc_i.data.eq(pc_i) comb += issuer.go_insn_i.eq(go_insn_i) @@ -94,6 +89,13 @@ class TestRunner(FHDLTestCase): def process(): for test in self.test_data: + + # get core going + yield core.core_start_i.eq(1) + yield + yield core.core_start_i.eq(0) + yield Settle() + print(test.name) program = test.program self.subTest(test.name) @@ -132,6 +134,7 @@ class TestRunner(FHDLTestCase): yield yield issuer.pc_i.ok.eq(0) # don't change PC from now on yield go_insn_i.eq(0) # and don't issue a new insn + yield Settle() # wait until executed yield from wait_for_busy_hi(core) @@ -150,6 +153,10 @@ class TestRunner(FHDLTestCase): # Memory check yield from check_sim_memory(self, l0, sim, code) + terminated = yield core.core_terminated_o + if terminated: + break + sim.add_sync_process(process) with sim.write_vcd("issuer_simulator.vcd", traces=[]): @@ -159,12 +166,13 @@ class TestRunner(FHDLTestCase): if __name__ == "__main__": unittest.main(exit=False) suite = unittest.TestSuite() - suite.addTest(TestRunner(GeneralTestCases.test_data)) + suite.addTest(TestRunner(AttnTestCase.test_data)) + #suite.addTest(TestRunner(GeneralTestCases.test_data)) #suite.addTest(TestRunner(LDSTTestCase.test_data)) #suite.addTest(TestRunner(CRTestCase.test_data)) #suite.addTest(TestRunner(ShiftRotTestCase.test_data)) #suite.addTest(TestRunner(LogicalTestCase.test_data)) - #suite.addTest(TestRunner(ALUTestCase.test_data)) + suite.addTest(TestRunner(ALUTestCase.test_data)) #suite.addTest(TestRunner(BranchTestCase.test_data)) #suite.addTest(TestRunner(SPRTestCase.test_data)) -- 2.30.2