From e877f715cad29745cf0257c3f73315c2f1a1402d Mon Sep 17 00:00:00 2001 From: Giacomo Travaglini Date: Sat, 18 Jul 2020 14:25:26 +0100 Subject: [PATCH] dev-arm: Check for security attribute when writing to ICFGR registers This is matching the GICD_ICFGR read; a non secure access to a secure interrupt should be treated as RAZ/WI Change-Id: I9e92e03c13fe0474ed139b0ed22cebd5847b9109 Signed-off-by: Giacomo Travaglini Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/31615 Reviewed-by: Andreas Sandberg Maintainer: Andreas Sandberg Tested-by: kokoro --- src/dev/arm/gic_v3_distributor.cc | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/src/dev/arm/gic_v3_distributor.cc b/src/dev/arm/gic_v3_distributor.cc index 485ba7284..f8605da27 100644 --- a/src/dev/arm/gic_v3_distributor.cc +++ b/src/dev/arm/gic_v3_distributor.cc @@ -743,6 +743,11 @@ Gicv3Distributor::write(Addr addr, uint64_t data, size_t size, for (int i = 0, int_id = first_intid; i < 8 * size && int_id < itLines; i = i + 2, int_id++) { + + if (nsAccessToSecInt(int_id, is_secure_access)) { + continue; + } + irqConfig[int_id] = data & (0x2 << i) ? Gicv3::INT_EDGE_TRIGGERED : Gicv3::INT_LEVEL_SENSITIVE; -- 2.30.2