From e88083870d93894e5bc263dd90af6885c5c705a2 Mon Sep 17 00:00:00 2001 From: lkcl Date: Sun, 24 Jan 2021 13:23:56 +0000 Subject: [PATCH] --- openpower/sv/ldst.mdwn | 5 +++-- 1 file changed, 3 insertions(+), 2 deletions(-) diff --git a/openpower/sv/ldst.mdwn b/openpower/sv/ldst.mdwn index 5f554a59f..1db2ced51 100644 --- a/openpower/sv/ldst.mdwn +++ b/openpower/sv/ldst.mdwn @@ -159,7 +159,7 @@ The modes for `RA+RB` indexed version are slightly different: A summary of the effect of Vectorisation of src or dest: imm(RA) RT.v RA.v no stride allowed - imm(RA) RY.s RA.v no stride allowed + imm(RA) RT.s RA.v no stride allowed imm(RA) RT.v RA.s stride-select needed imm(RA) RT.s RA.s not vectorised RA,RB RT.v RA/RB.v ffirst banned @@ -295,6 +295,7 @@ permutations of vector selection, to identify above asm-syntax: sv.ld r#.v, ofst(r#2.v) -> r#2 is a vector of addresses imm(RA) RT.s RA.v nonstrided sv.ld r#, ofst(r#2.v) -> r#2 is a vector of addresses + (dest r# is scalar) -> VSELECT mode imm(RA) RT.v RA.s fixed stride: unit or element sv.ld r#.v, ofst(r#2).v -> the whole vector is at ofst+r#2 mem 0 1 2 @@ -305,7 +306,7 @@ permutations of vector selection, to identify above asm-syntax: imm(RA) RT.s RA.s not vectorised sv.ld r#, ofst(r#2) -TODO: indexed mode +indexed mode: RA,RB RT.v RA.v RB.v sv.ldx r#.v, r#2, r#3.v -> whole vector at r#2+r#3 -- 2.30.2