From e8b9ea79376d1fe69ee747e026a366d03ad5d5e6 Mon Sep 17 00:00:00 2001 From: Konstantinos Margaritis Date: Wed, 27 Jul 2022 08:43:42 +0000 Subject: [PATCH] fix wrong shift in fmvis, use correct immediates in test --- src/openpower/sv/trans/svp64.py | 6 +++--- src/openpower/test/alu/fmvis_cases.py | 6 +++--- 2 files changed, 6 insertions(+), 6 deletions(-) diff --git a/src/openpower/sv/trans/svp64.py b/src/openpower/sv/trans/svp64.py index f2361333..a285d1a3 100644 --- a/src/openpower/sv/trans/svp64.py +++ b/src/openpower/sv/trans/svp64.py @@ -344,12 +344,12 @@ def fmvis(fields): # first split imm into d1, d0 and d2. sigh d2 = (imm & 1) # LSB (0) d1 = (imm >> 1) & 0b11111 # bits 1-5 - d0 = (imm >> 6) # MSBs 6-15 + d0 = (imm >> 5) # MSBs 6-15 return instruction( (PO , 0 , 5), (FRS, 6 , 10), - (d1, 11, 15), - (d0, 16, 26), + (d1, 11, 15), + (d0, 16, 26), (XO , 27, 30), (d2 , 31, 31), ) diff --git a/src/openpower/test/alu/fmvis_cases.py b/src/openpower/test/alu/fmvis_cases.py index 7562cd1e..e698ed36 100644 --- a/src/openpower/test/alu/fmvis_cases.py +++ b/src/openpower/test/alu/fmvis_cases.py @@ -14,14 +14,14 @@ class FMVISTestCase(TestAccumulatorBase): def case_0_fmvis(self): lst = SVP64Asm(["fmvis 5, 0x4000", # 2.0 - "fmvis 6, 0x2122", + "fmvis 6, 0x4048", # 3.125 "fmvis 7, 0x3E80", # 0.25 ]) lst = list(lst) - expected_fprs = [0] * 64 + expected_fprs = [0] * 32 expected_fprs[5] = 0x4000000000000000 # 2.0 in FP64 form - expected_fprs[6] = 0x2122000000000000 + expected_fprs[6] = 0x4009000000000000 # 3.125 in FP64 form expected_fprs[7] = 0x3FD0000000000000 # 0.25 in FP64 form e = ExpectedState(pc=0xc, # 3 instructions so 3x4=0xc fp_regs=expected_fprs) # expected results -- 2.30.2