From e8cca57a3f709b9b8bce0b25290d6d8091bbdda7 Mon Sep 17 00:00:00 2001 From: Rob Clark Date: Sun, 16 Feb 2014 07:41:59 -0500 Subject: [PATCH] freedreno/a3xx/compiler: fix RA typo Was supposed to be a '+', otherwise we end up with a negative offset and choosing registers below the assigned range. This seems to fix the scheduling mystery "solved" by adding in extra delay slots. Signed-off-by: Rob Clark --- src/gallium/drivers/freedreno/a3xx/ir3_depth.c | 6 +++--- src/gallium/drivers/freedreno/a3xx/ir3_ra.c | 2 +- 2 files changed, 4 insertions(+), 4 deletions(-) diff --git a/src/gallium/drivers/freedreno/a3xx/ir3_depth.c b/src/gallium/drivers/freedreno/a3xx/ir3_depth.c index 452257884df..1715f1917f0 100644 --- a/src/gallium/drivers/freedreno/a3xx/ir3_depth.c +++ b/src/gallium/drivers/freedreno/a3xx/ir3_depth.c @@ -69,13 +69,13 @@ int ir3_delayslots(struct ir3_instruction *assigner, /* assigner must be alu: */ if (is_flow(consumer) || is_sfu(consumer) || is_tex(consumer)) { - return 8; + return 6; } else if ((consumer->category == 3) && is_mad(consumer->opc) && (n == 2)) { /* special case, 3rd src to cat3 not required on first cycle */ - return 2; + return 1; } else { - return 5; + return 3; } } diff --git a/src/gallium/drivers/freedreno/a3xx/ir3_ra.c b/src/gallium/drivers/freedreno/a3xx/ir3_ra.c index 22c58e6c9ad..5bc1e2f1619 100644 --- a/src/gallium/drivers/freedreno/a3xx/ir3_ra.c +++ b/src/gallium/drivers/freedreno/a3xx/ir3_ra.c @@ -306,7 +306,7 @@ static void ra_calc_src_fanin(struct ir3_visitor *v, { struct ra_calc_visitor *c = ra_calc_visitor(v); unsigned srcn = ir3_instr_regno(instr, reg) - 1; - c->a.off -= srcn; + c->a.off += srcn; c->a.num += srcn; c->a.num = MAX2(c->a.num, instr->regs_count - 1); } -- 2.30.2