From e8db842538e5533d946015fdb7cd3e4cc360911d Mon Sep 17 00:00:00 2001 From: Sebastien Bourdeauducq Date: Fri, 8 Aug 2014 19:14:15 +0800 Subject: [PATCH] s6ddrphy: fix DFI interface data width computation --- misoclib/sdramphy/s6ddrphy.py | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/misoclib/sdramphy/s6ddrphy.py b/misoclib/sdramphy/s6ddrphy.py index bdd9d6be..d4f9aa2f 100644 --- a/misoclib/sdramphy/s6ddrphy.py +++ b/misoclib/sdramphy/s6ddrphy.py @@ -42,7 +42,7 @@ class S6DDRPHY(Module): write_latency=0 ) - self.dfi = Interface(a, ba, nphases*d, nphases) + self.dfi = Interface(a, ba, self.phy_settings.dfi_d, nphases) self.clk4x_wr_strb = Signal() self.clk4x_rd_strb = Signal() -- 2.30.2