From e8e10da8650ff797faaad320fbd8b442a4bc4f0e Mon Sep 17 00:00:00 2001 From: Luke Kenneth Casson Leighton Date: Fri, 22 May 2020 20:06:41 +0100 Subject: [PATCH] remove sticky overflow from Shift Rot pipeline --- src/soc/fu/shift_rot/main_stage.py | 5 ++--- src/soc/fu/shift_rot/pipe_data.py | 6 +----- src/soc/fu/shift_rot/pipeline.py | 4 ++-- src/soc/fu/shift_rot/test/test_pipe_caller.py | 2 -- 4 files changed, 5 insertions(+), 12 deletions(-) diff --git a/src/soc/fu/shift_rot/main_stage.py b/src/soc/fu/shift_rot/main_stage.py index 10949c55..16b45530 100644 --- a/src/soc/fu/shift_rot/main_stage.py +++ b/src/soc/fu/shift_rot/main_stage.py @@ -4,7 +4,7 @@ # output stage from nmigen import (Module, Signal, Cat, Repl, Mux, Const) from nmutil.pipemodbase import PipeModBase -from soc.fu.alu.pipe_data import ALUOutputData +from soc.fu.logical.pipe_data import LogicalOutputData from soc.fu.shift_rot.pipe_data import ShiftRotInputData from ieee754.part.partsig import PartitionedSignal from soc.decoder.power_enums import InternalOp @@ -24,7 +24,7 @@ class ShiftRotMainStage(PipeModBase): return ShiftRotInputData(self.pspec) def ospec(self): - return ALUOutputData(self.pspec) # TODO: ALUIntermediateData + return LogicalOutputData(self.pspec) def elaborate(self, platform): m = Module() @@ -74,7 +74,6 @@ class ShiftRotMainStage(PipeModBase): ###### sticky overflow and context, both pass-through ##### - comb += self.o.xer_so.data.eq(self.i.xer_so) comb += self.o.ctx.eq(self.i.ctx) return m diff --git a/src/soc/fu/shift_rot/pipe_data.py b/src/soc/fu/shift_rot/pipe_data.py index 1375ae0a..ed3cd14d 100644 --- a/src/soc/fu/shift_rot/pipe_data.py +++ b/src/soc/fu/shift_rot/pipe_data.py @@ -11,14 +11,12 @@ class ShiftRotInputData(IntegerData): regspec = [('INT', 'a', '0:63'), ('INT', 'rs', '0:63'), ('INT', 'rb', '0:63'), - ('XER', 'xer_so', '32'), ('XER', 'xer_ca', '34,45')] def __init__(self, pspec): super().__init__(pspec) self.a = Signal(64, reset_less=True) # RA self.rs = Signal(64, reset_less=True) # RS self.rb = Signal(64, reset_less=True) # RB/immediate - self.xer_so = Signal(reset_less=True) # XER bit 32: SO self.xer_ca = Signal(2, reset_less=True) # XER bit 34/45: CA/CA32 def __iter__(self): @@ -27,14 +25,12 @@ class ShiftRotInputData(IntegerData): yield self.rs yield self.rb yield self.xer_ca - yield self.xer_so def eq(self, i): lst = super().eq(i) return lst + [self.rs.eq(i.rs), self.a.eq(i.a), self.rb.eq(i.rb), - self.xer_ca.eq(i.xer_ca), - self.xer_so.eq(i.xer_so)] + self.xer_ca.eq(i.xer_ca) ] # TODO: replace CompALUOpSubset with CompShiftRotOpSubset diff --git a/src/soc/fu/shift_rot/pipeline.py b/src/soc/fu/shift_rot/pipeline.py index 316fb832..0449d37d 100644 --- a/src/soc/fu/shift_rot/pipeline.py +++ b/src/soc/fu/shift_rot/pipeline.py @@ -2,13 +2,13 @@ from nmutil.singlepipe import ControlBase from nmutil.pipemodbase import PipeModBaseChain from soc.fu.shift_rot.input_stage import ShiftRotInputStage from soc.fu.shift_rot.main_stage import ShiftRotMainStage -from soc.fu.alu.output_stage import ALUOutputStage +from soc.fu.logical.output_stage import LogicalOutputStage class ShiftRotStages(PipeModBaseChain): def get_chain(self): inp = ShiftRotInputStage(self.pspec) main = ShiftRotMainStage(self.pspec) - out = ALUOutputStage(self.pspec) + out = LogicalOutputStage(self.pspec) return [inp, main, out] diff --git a/src/soc/fu/shift_rot/test/test_pipe_caller.py b/src/soc/fu/shift_rot/test/test_pipe_caller.py index fb370525..2d6fb8e1 100644 --- a/src/soc/fu/shift_rot/test/test_pipe_caller.py +++ b/src/soc/fu/shift_rot/test/test_pipe_caller.py @@ -63,8 +63,6 @@ def set_extra_alu_inputs(alu, dec2, sim): carry32 = 1 if sim.spr['XER'][XER_bits['CA32']] else 0 yield alu.p.data_i.xer_ca[0].eq(carry) yield alu.p.data_i.xer_ca[1].eq(carry32) - so = 1 if sim.spr['XER'][XER_bits['SO']] else 0 - yield alu.p.data_i.xer_so.eq(so) # This test bench is a bit different than is usual. Initially when I -- 2.30.2