From e9147bfab40d26fb8f8c0794e9a3fdcf14ca57dd Mon Sep 17 00:00:00 2001 From: Ben Skeggs Date: Wed, 6 Feb 2008 00:26:49 +1100 Subject: [PATCH] nv40: cleanup state handling a bit --- src/mesa/pipe/nouveau/nouveau_stateobj.h | 139 +++++++ src/mesa/pipe/nv40/nv40_context.h | 18 +- src/mesa/pipe/nv40/nv40_fragprog.c | 18 +- src/mesa/pipe/nv40/nv40_fragtex.c | 38 +- src/mesa/pipe/nv40/nv40_state.c | 464 ++++++++++++----------- src/mesa/pipe/nv40/nv40_state.h | 68 +--- src/mesa/pipe/nv40/nv40_state_emit.c | 70 +--- src/mesa/pipe/nv40/nv40_vbo.c | 81 ++-- 8 files changed, 462 insertions(+), 434 deletions(-) create mode 100644 src/mesa/pipe/nouveau/nouveau_stateobj.h diff --git a/src/mesa/pipe/nouveau/nouveau_stateobj.h b/src/mesa/pipe/nouveau/nouveau_stateobj.h new file mode 100644 index 00000000000..8dfc0e9e9ac --- /dev/null +++ b/src/mesa/pipe/nouveau/nouveau_stateobj.h @@ -0,0 +1,139 @@ +#ifndef __NOUVEAU_STATEOBJ_H__ +#define __NOUVEAU_STATEOBJ_H__ + +struct nouveau_stateobj_reloc { + struct pipe_buffer *bo; + + unsigned offset; + unsigned packet; + + unsigned data; + unsigned flags; + unsigned vor; + unsigned tor; +}; + +struct nouveau_stateobj { + int refcount; + + unsigned *push; + struct nouveau_stateobj_reloc *reloc; + + unsigned *cur; + unsigned cur_packet; + unsigned cur_reloc; +}; + +static inline struct nouveau_stateobj * +so_new(unsigned push, unsigned reloc) +{ + struct nouveau_stateobj *so; + + so = malloc(sizeof(struct nouveau_stateobj)); + so->refcount = 0; + so->push = malloc(sizeof(unsigned) * push); + so->reloc = malloc(sizeof(struct nouveau_stateobj_reloc) * reloc); + + so->cur = so->push; + so->cur_reloc = so->cur_packet = 0; + + return so; +} + +static inline void +so_ref(struct nouveau_stateobj *ref, struct nouveau_stateobj **pso) +{ + struct nouveau_stateobj *so; + + so = *pso; + if (so) { + if (--so->refcount <= 0) { + free(so->push); + free(so->reloc); + free(so); + } + *pso = NULL; + } + + if (ref) { + ref->refcount++; + *pso = ref; + } +} + +static inline void +so_data(struct nouveau_stateobj *so, unsigned data) +{ + (*so->cur++) = (data); + so->cur_packet += 4; +} + +static inline void +so_method(struct nouveau_stateobj *so, struct nouveau_grobj *gr, + unsigned mthd, unsigned size) +{ + so->cur_packet = (gr->subc << 13) | (1 << 18) | (mthd - 4); + so_data(so, (gr->subc << 13) | (size << 18) | mthd); +} + +static inline void +so_reloc(struct nouveau_stateobj *so, struct pipe_buffer *bo, + unsigned data, unsigned flags, unsigned vor, unsigned tor) +{ + struct nouveau_stateobj_reloc *r = &so->reloc[so->cur_reloc++]; + + r->bo = bo; + r->offset = so->cur - so->push; + r->packet = so->cur_packet; + r->data = data; + r->flags = flags; + r->vor = vor; + r->tor = tor; + so_data(so, data); +} + +static inline void +so_emit(struct nouveau_winsys *nvws, struct nouveau_stateobj *so) +{ + struct nouveau_pushbuf *pb = nvws->channel->pushbuf; + unsigned nr, i; + + nr = so->cur - so->push; + if (pb->remaining < nr) + nvws->push_flush(nvws->channel, nr); + pb->remaining -= nr; + + memcpy(pb->cur, so->push, nr * 4); + for (i = 0; i < so->cur_reloc; i++) { + struct nouveau_stateobj_reloc *r = &so->reloc[i]; + + nvws->push_reloc(nvws->channel, pb->cur + r->offset, r->bo, + r->data, r->flags, r->vor, r->tor); + } + pb->cur += nr; +} + +static inline void +so_emit_reloc_markers(struct nouveau_winsys *nvws, struct nouveau_stateobj *so) +{ + struct nouveau_pushbuf *pb = nvws->channel->pushbuf; + unsigned i; + + i = so->cur_reloc << 1; + if (nvws->channel->pushbuf->remaining < i) + nvws->push_flush(nvws->channel, i); + nvws->channel->pushbuf->remaining -= i; + + for (i = 0; i < so->cur_reloc; i++) { + struct nouveau_stateobj_reloc *r = &so->reloc[i]; + + nvws->push_reloc(nvws->channel, pb->cur++, r->bo, r->packet, + (r->flags & + (NOUVEAU_BO_VRAM | NOUVEAU_BO_GART)) | + NOUVEAU_BO_DUMMY, 0, 0); + nvws->push_reloc(nvws->channel, pb->cur++, r->bo, r->data, + r->flags | NOUVEAU_BO_DUMMY, r->vor, r->tor); + } +} + +#endif diff --git a/src/mesa/pipe/nv40/nv40_context.h b/src/mesa/pipe/nv40/nv40_context.h index 2d069619d7c..1a31f00ad6a 100644 --- a/src/mesa/pipe/nv40/nv40_context.h +++ b/src/mesa/pipe/nv40/nv40_context.h @@ -13,6 +13,7 @@ #define NOUVEAU_PUSH_CONTEXT(ctx) \ struct nv40_context *ctx = nv40 #include "pipe/nouveau/nouveau_push.h" +#include "pipe/nouveau/nouveau_stateobj.h" #include "nv40_state.h" @@ -47,20 +48,9 @@ struct nv40_context { unsigned fp_samplers; unsigned vp_samplers; - uint32_t rt_enable; - struct pipe_buffer *rt[4]; - struct pipe_buffer *zeta; - - struct { - struct pipe_buffer *buffer; - uint32_t format; - } tex[16]; - - unsigned vb_enable; - struct { - struct pipe_buffer *buffer; - unsigned delta; - } vb[16]; + struct nouveau_stateobj *so_framebuffer; + struct nouveau_stateobj *so_fragtex[16]; + struct nouveau_stateobj *so_vtxbuf; struct { struct nouveau_resource *exec_heap; diff --git a/src/mesa/pipe/nv40/nv40_fragprog.c b/src/mesa/pipe/nv40/nv40_fragprog.c index 667eb89cb24..e650c975413 100644 --- a/src/mesa/pipe/nv40/nv40_fragprog.c +++ b/src/mesa/pipe/nv40/nv40_fragprog.c @@ -759,6 +759,7 @@ void nv40_fragprog_bind(struct nv40_context *nv40, struct nv40_fragment_program *fp) { struct pipe_winsys *ws = nv40->pipe.winsys; + struct nouveau_stateobj *so; int i; if (!fp->translated) { @@ -815,13 +816,16 @@ nv40_fragprog_bind(struct nv40_context *nv40, struct nv40_fragment_program *fp) fp->on_hw = TRUE; } - BEGIN_RING(curie, NV40TCL_FP_ADDRESS, 1); - OUT_RELOC (fp->buffer, 0, NOUVEAU_BO_VRAM | - NOUVEAU_BO_GART | NOUVEAU_BO_RD | NOUVEAU_BO_LOW | - NOUVEAU_BO_OR, NV40TCL_FP_ADDRESS_DMA0, - NV40TCL_FP_ADDRESS_DMA1); - BEGIN_RING(curie, NV40TCL_FP_CONTROL, 1); - OUT_RING (fp->fp_control); + so = so_new(4, 1); + so_method(so, nv40->curie, NV40TCL_FP_ADDRESS, 1); + so_reloc (so, fp->buffer, 0, NOUVEAU_BO_VRAM | NOUVEAU_BO_GART | + NOUVEAU_BO_RD | NOUVEAU_BO_LOW | NOUVEAU_BO_OR, + NV40TCL_FP_ADDRESS_DMA0, NV40TCL_FP_ADDRESS_DMA1); + so_method(so, nv40->curie, NV40TCL_FP_CONTROL, 1); + so_data (so, fp->fp_control); + + so_emit(nv40->nvws, so); + so_ref(so, &fp->so); nv40->fragprog.active = fp; } diff --git a/src/mesa/pipe/nv40/nv40_fragtex.c b/src/mesa/pipe/nv40/nv40_fragtex.c index 7c5ecd5c566..283d49704af 100644 --- a/src/mesa/pipe/nv40/nv40_fragtex.c +++ b/src/mesa/pipe/nv40/nv40_fragtex.c @@ -59,8 +59,10 @@ nv40_fragtex_build(struct nv40_context *nv40, int unit) struct nv40_miptree *nv40mt = nv40->tex_miptree[unit]; struct pipe_texture *pt = &nv40mt->base; struct nv40_texture_format *tf; + struct nouveau_stateobj *so; uint32_t txf, txs, txp; int swizzled = 0; /*XXX: implement in region code? */ + unsigned tex_flags = NOUVEAU_BO_VRAM | NOUVEAU_BO_GART | NOUVEAU_BO_RD; tf = nv40_fragtex_format(pt->format); if (!tf) @@ -101,25 +103,24 @@ nv40_fragtex_build(struct nv40_context *nv40, int unit) txs = tf->swizzle; - nv40->tex[unit].buffer = nv40mt->buffer; - nv40->tex[unit].format = txf; - - BEGIN_RING(curie, NV40TCL_TEX_OFFSET(unit), 8); - OUT_RELOCl(nv40->tex[unit].buffer, 0, NOUVEAU_BO_VRAM | - NOUVEAU_BO_GART | NOUVEAU_BO_RD); - OUT_RELOCd(nv40->tex[unit].buffer, nv40->tex[unit].format, - NOUVEAU_BO_VRAM | NOUVEAU_BO_GART | NOUVEAU_BO_RD | - NOUVEAU_BO_OR, NV40TCL_TEX_FORMAT_DMA0, - NV40TCL_TEX_FORMAT_DMA1); - OUT_RING (ps->wrap); - OUT_RING (NV40TCL_TEX_ENABLE_ENABLE | ps->en | + so = so_new(16, 2); + so_method(so, nv40->curie, NV40TCL_TEX_OFFSET(unit), 8); + so_reloc (so, nv40mt->buffer, 0, tex_flags | NOUVEAU_BO_LOW, 0, 0); + so_reloc (so, nv40mt->buffer, txf, tex_flags | NOUVEAU_BO_OR, + NV40TCL_TEX_FORMAT_DMA0, NV40TCL_TEX_FORMAT_DMA1); + so_data (so, ps->wrap); + so_data (so, NV40TCL_TEX_ENABLE_ENABLE | ps->en | (0x00078000) /* mipmap related? */); - OUT_RING (txs); - OUT_RING (ps->filt | 0x3fd6 /*voodoo*/); - OUT_RING ((pt->width[0] << NV40TCL_TEX_SIZE0_W_SHIFT) | pt->height[0]); - OUT_RING (ps->bcol); - BEGIN_RING(curie, NV40TCL_TEX_SIZE1(unit), 1); - OUT_RING ((pt->depth[0] << NV40TCL_TEX_SIZE1_DEPTH_SHIFT) | txp); + so_data (so, txs); + so_data (so, ps->filt | 0x3fd6 /*voodoo*/); + so_data (so, (pt->width[0] << NV40TCL_TEX_SIZE0_W_SHIFT) | + pt->height[0]); + so_data (so, ps->bcol); + so_method(so, nv40->curie, NV40TCL_TEX_SIZE1(unit), 1); + so_data (so, (pt->depth[0] << NV40TCL_TEX_SIZE1_DEPTH_SHIFT) | txp); + + so_emit(nv40->nvws, so); + so_ref (so, &nv40->so_fragtex[unit]); } void @@ -133,6 +134,7 @@ nv40_fragtex_bind(struct nv40_context *nv40) unit = ffs(samplers) - 1; samplers &= ~(1 << unit); + so_ref(NULL, &nv40->so_fragtex[unit]); BEGIN_RING(curie, NV40TCL_TEX_ENABLE(unit), 1); OUT_RING (0); } diff --git a/src/mesa/pipe/nv40/nv40_state.c b/src/mesa/pipe/nv40/nv40_state.c index bb435b106b4..125134afdcd 100644 --- a/src/mesa/pipe/nv40/nv40_state.c +++ b/src/mesa/pipe/nv40/nv40_state.c @@ -9,59 +9,59 @@ static void * nv40_blend_state_create(struct pipe_context *pipe, const struct pipe_blend_state *cso) { - struct nv40_blend_state *cb; - - cb = malloc(sizeof(struct nv40_blend_state)); - - cb->b_enable = cso->blend_enable ? 1 : 0; - cb->b_srcfunc = ((nvgl_blend_func(cso->alpha_src_factor)<<16) | - (nvgl_blend_func(cso->rgb_src_factor))); - cb->b_dstfunc = ((nvgl_blend_func(cso->alpha_dst_factor)<<16) | - (nvgl_blend_func(cso->rgb_dst_factor))); - cb->b_eqn = ((nvgl_blend_eqn(cso->alpha_func) << 16) | - (nvgl_blend_eqn(cso->rgb_func))); + struct nv40_context *nv40 = nv40_context(pipe); + struct nouveau_stateobj *so = so_new(16, 0); + + if (cso->blend_enable) { + so_method(so, nv40->curie, NV40TCL_BLEND_ENABLE, 3); + so_data (so, 1); + so_data (so, (nvgl_blend_func(cso->alpha_src_factor) << 16) | + nvgl_blend_func(cso->rgb_src_factor)); + so_data (so, nvgl_blend_func(cso->alpha_dst_factor) << 16 | + nvgl_blend_func(cso->rgb_dst_factor)); + so_method(so, nv40->curie, NV40TCL_BLEND_EQUATION, 1); + so_data (so, nvgl_blend_eqn(cso->alpha_func) << 16 | + nvgl_blend_eqn(cso->rgb_func)); + } else { + so_method(so, nv40->curie, NV40TCL_BLEND_ENABLE, 1); + so_data (so, 0); + } - cb->l_enable = cso->logicop_enable ? 1 : 0; - cb->l_op = nvgl_logicop_func(cso->logicop_func); + so_method(so, nv40->curie, NV40TCL_COLOR_MASK, 1); + so_data (so, (((cso->colormask & PIPE_MASK_A) ? (0x01 << 24) : 0) | + ((cso->colormask & PIPE_MASK_R) ? (0x01 << 16) : 0) | + ((cso->colormask & PIPE_MASK_G) ? (0x01 << 8) : 0) | + ((cso->colormask & PIPE_MASK_B) ? (0x01 << 0) : 0))); - cb->c_mask = (((cso->colormask & PIPE_MASK_A) ? (0x01<<24) : 0) | - ((cso->colormask & PIPE_MASK_R) ? (0x01<<16) : 0) | - ((cso->colormask & PIPE_MASK_G) ? (0x01<< 8) : 0) | - ((cso->colormask & PIPE_MASK_B) ? (0x01<< 0) : 0)); + if (cso->logicop_enable) { + so_method(so, nv40->curie, NV40TCL_COLOR_LOGIC_OP_ENABLE, 2); + so_data (so, 1); + so_data (so, nvgl_logicop_func(cso->logicop_func)); + } else { + so_method(so, nv40->curie, NV40TCL_COLOR_LOGIC_OP_ENABLE, 1); + so_data (so, 0); + } - cb->d_enable = cso->dither ? 1 : 0; + so_method(so, nv40->curie, NV40TCL_DITHER_ENABLE, 1); + so_data (so, cso->dither ? 1 : 0); - return (void *)cb; + return (void *)so; } static void nv40_blend_state_bind(struct pipe_context *pipe, void *hwcso) { struct nv40_context *nv40 = nv40_context(pipe); - struct nv40_blend_state *cb = hwcso; - BEGIN_RING(curie, NV40TCL_DITHER_ENABLE, 1); - OUT_RING (cb->d_enable); - - BEGIN_RING(curie, NV40TCL_BLEND_ENABLE, 3); - OUT_RING (cb->b_enable); - OUT_RING (cb->b_srcfunc); - OUT_RING (cb->b_dstfunc); - BEGIN_RING(curie, NV40TCL_BLEND_EQUATION, 1); - OUT_RING (cb->b_eqn); - - BEGIN_RING(curie, NV40TCL_COLOR_MASK, 1); - OUT_RING (cb->c_mask); - - BEGIN_RING(curie, NV40TCL_COLOR_LOGIC_OP_ENABLE, 2); - OUT_RING (cb->l_enable); - OUT_RING (cb->l_op); + so_emit(nv40->nvws, hwcso); } static void nv40_blend_state_delete(struct pipe_context *pipe, void *hwcso) { - free(hwcso); + struct nouveau_stateobj *so = hwcso; + + so_ref(NULL, &so); } @@ -261,8 +261,8 @@ static void * nv40_rasterizer_state_create(struct pipe_context *pipe, const struct pipe_rasterizer_state *cso) { - struct nv40_rasterizer_state *rs; - int i; + struct nv40_context *nv40 = nv40_context(pipe); + struct nouveau_stateobj *so = so_new(32, 0); /*XXX: ignored: * light_twoside @@ -272,165 +272,163 @@ nv40_rasterizer_state_create(struct pipe_context *pipe, * multisample * offset_units / offset_scale */ - rs = malloc(sizeof(struct nv40_rasterizer_state)); - - rs->shade_model = cso->flatshade ? 0x1d00 : 0x1d01; - rs->line_width = (unsigned char)(cso->line_width * 8.0) & 0xff; - rs->line_smooth_en = cso->line_smooth ? 1 : 0; - rs->line_stipple_en = cso->line_stipple_enable ? 1 : 0; - rs->line_stipple = (cso->line_stipple_pattern << 16) | - cso->line_stipple_factor; + so_method(so, nv40->curie, NV40TCL_SHADE_MODEL, 1); + so_data (so, cso->flatshade ? NV40TCL_SHADE_MODEL_FLAT : + NV40TCL_SHADE_MODEL_SMOOTH); - rs->point_size = *(uint32_t*)&cso->point_size; + so_method(so, nv40->curie, NV40TCL_LINE_WIDTH, 2); + so_data (so, (unsigned char)(cso->line_width * 8.0) & 0xff); + so_data (so, cso->line_smooth ? 1 : 0); + so_method(so, nv40->curie, NV40TCL_LINE_STIPPLE_ENABLE, 2); + so_data (so, cso->line_stipple_enable ? 1 : 0); + so_data (so, (cso->line_stipple_pattern << 16) | + cso->line_stipple_factor); - rs->poly_smooth_en = cso->poly_smooth ? 1 : 0; - rs->poly_stipple_en = cso->poly_stipple_enable ? 1 : 0; + so_method(so, nv40->curie, NV40TCL_POINT_SIZE, 1); + so_data (so, fui(cso->point_size)); + so_method(so, nv40->curie, NV40TCL_POLYGON_MODE_FRONT, 6); if (cso->front_winding == PIPE_WINDING_CCW) { - rs->front_face = NV40TCL_FRONT_FACE_CCW; - rs->poly_mode_front = nvgl_polygon_mode(cso->fill_ccw); - rs->poly_mode_back = nvgl_polygon_mode(cso->fill_cw); + so_data(so, nvgl_polygon_mode(cso->fill_ccw)); + so_data(so, nvgl_polygon_mode(cso->fill_cw)); + switch (cso->cull_mode) { + case PIPE_WINDING_CCW: + so_data(so, NV40TCL_CULL_FACE_FRONT); + break; + case PIPE_WINDING_CW: + so_data(so, NV40TCL_CULL_FACE_BACK); + break; + case PIPE_WINDING_BOTH: + so_data(so, NV40TCL_CULL_FACE_FRONT_AND_BACK); + break; + default: + so_data(so, 0); + break; + } + so_data(so, NV40TCL_FRONT_FACE_CCW); } else { - rs->front_face = NV40TCL_FRONT_FACE_CW; - rs->poly_mode_front = nvgl_polygon_mode(cso->fill_cw); - rs->poly_mode_back = nvgl_polygon_mode(cso->fill_ccw); + so_data(so, nvgl_polygon_mode(cso->fill_cw)); + so_data(so, nvgl_polygon_mode(cso->fill_ccw)); + switch (cso->cull_mode) { + case PIPE_WINDING_CCW: + so_data(so, NV40TCL_CULL_FACE_BACK); + break; + case PIPE_WINDING_CW: + so_data(so, NV40TCL_CULL_FACE_FRONT); + break; + case PIPE_WINDING_BOTH: + so_data(so, NV40TCL_CULL_FACE_FRONT_AND_BACK); + break; + default: + so_data(so, 0); + break; + } + so_data(so, NV40TCL_FRONT_FACE_CW); } + so_data(so, cso->poly_smooth ? 1 : 0); + so_data(so, cso->cull_mode != PIPE_WINDING_NONE ? 1 : 0); - switch (cso->cull_mode) { - case PIPE_WINDING_CCW: - rs->cull_face_en = 1; - if (cso->front_winding == PIPE_WINDING_CCW) - rs->cull_face = NV40TCL_CULL_FACE_FRONT; - else - rs->cull_face = NV40TCL_CULL_FACE_BACK; - break; - case PIPE_WINDING_CW: - rs->cull_face_en = 1; - if (cso->front_winding == PIPE_WINDING_CW) - rs->cull_face = NV40TCL_CULL_FACE_FRONT; - else - rs->cull_face = NV40TCL_CULL_FACE_BACK; - break; - case PIPE_WINDING_BOTH: - rs->cull_face_en = 1; - rs->cull_face = NV40TCL_CULL_FACE_FRONT_AND_BACK; - break; - case PIPE_WINDING_NONE: - default: - rs->cull_face_en = 0; - rs->cull_face = 0; - break; - } + so_method(so, nv40->curie, NV40TCL_POLYGON_STIPPLE_ENABLE, 1); + so_data (so, cso->poly_stipple_enable ? 1 : 0); + so_method(so, nv40->curie, NV40TCL_POINT_SPRITE, 1); if (cso->point_sprite) { - rs->point_sprite = (1 << 0); + unsigned psctl = (1 << 0), i; + for (i = 0; i < 8; i++) { if (cso->sprite_coord_mode[i] != PIPE_SPRITE_COORD_NONE) - rs->point_sprite |= (1 << (8 + i)); + psctl |= (1 << (8 + i)); } + + so_data(so, psctl); } else { - rs->point_sprite = 0; + so_data(so, 0); } - return (void *)rs; + return (void *)so; } static void nv40_rasterizer_state_bind(struct pipe_context *pipe, void *hwcso) { struct nv40_context *nv40 = nv40_context(pipe); - struct nv40_rasterizer_state *rs = hwcso; - - BEGIN_RING(curie, NV40TCL_SHADE_MODEL, 1); - OUT_RING (rs->shade_model); - - BEGIN_RING(curie, NV40TCL_LINE_WIDTH, 2); - OUT_RING (rs->line_width); - OUT_RING (rs->line_smooth_en); - BEGIN_RING(curie, NV40TCL_LINE_STIPPLE_ENABLE, 2); - OUT_RING (rs->line_stipple_en); - OUT_RING (rs->line_stipple); - - BEGIN_RING(curie, NV40TCL_POINT_SIZE, 1); - OUT_RING (rs->point_size); - - BEGIN_RING(curie, NV40TCL_POLYGON_MODE_FRONT, 6); - OUT_RING (rs->poly_mode_front); - OUT_RING (rs->poly_mode_back); - OUT_RING (rs->cull_face); - OUT_RING (rs->front_face); - OUT_RING (rs->poly_smooth_en); - OUT_RING (rs->cull_face_en); - - BEGIN_RING(curie, NV40TCL_POLYGON_STIPPLE_ENABLE, 1); - OUT_RING (rs->poly_stipple_en); - - BEGIN_RING(curie, NV40TCL_POINT_SPRITE, 1); - OUT_RING (rs->point_sprite); + + so_emit(nv40->nvws, hwcso); } static void nv40_rasterizer_state_delete(struct pipe_context *pipe, void *hwcso) { - free(hwcso); -} + struct nouveau_stateobj *so = hwcso; -static void -nv40_translate_stencil(const struct pipe_depth_stencil_alpha_state *cso, - unsigned idx, struct nv40_stencil_push *hw) -{ - hw->enable = cso->stencil[idx].enabled ? 1 : 0; - hw->wmask = cso->stencil[idx].write_mask; - hw->func = nvgl_comparison_op(cso->stencil[idx].func); - hw->ref = cso->stencil[idx].ref_value; - hw->vmask = cso->stencil[idx].value_mask; - hw->fail = nvgl_stencil_op(cso->stencil[idx].fail_op); - hw->zfail = nvgl_stencil_op(cso->stencil[idx].zfail_op); - hw->zpass = nvgl_stencil_op(cso->stencil[idx].zpass_op); + so_ref(NULL, &so); } static void * nv40_depth_stencil_alpha_state_create(struct pipe_context *pipe, const struct pipe_depth_stencil_alpha_state *cso) { - struct nv40_depth_stencil_alpha_state *hw; - - hw = malloc(sizeof(struct nv40_depth_stencil_alpha_state)); - - hw->depth.func = nvgl_comparison_op(cso->depth.func); - hw->depth.write_enable = cso->depth.writemask ? 1 : 0; - hw->depth.test_enable = cso->depth.enabled ? 1 : 0; - - nv40_translate_stencil(cso, 0, &hw->stencil.front); - nv40_translate_stencil(cso, 1, &hw->stencil.back); + struct nv40_context *nv40 = nv40_context(pipe); + struct nouveau_stateobj *so = so_new(32, 0); + + so_method(so, nv40->curie, NV40TCL_DEPTH_FUNC, 3); + so_data (so, nvgl_comparison_op(cso->depth.func)); + so_data (so, cso->depth.writemask ? 1 : 0); + so_data (so, cso->depth.enabled ? 1 : 0); + + so_method(so, nv40->curie, NV40TCL_ALPHA_TEST_ENABLE, 3); + so_data (so, cso->alpha.enabled ? 1 : 0); + so_data (so, nvgl_comparison_op(cso->alpha.func)); + so_data (so, float_to_ubyte(cso->alpha.ref)); + + if (cso->stencil[0].enabled) { + so_method(so, nv40->curie, NV40TCL_STENCIL_FRONT_ENABLE, 8); + so_data (so, cso->stencil[0].enabled ? 1 : 0); + so_data (so, cso->stencil[0].write_mask); + so_data (so, nvgl_comparison_op(cso->stencil[0].func)); + so_data (so, cso->stencil[0].ref_value); + so_data (so, cso->stencil[0].value_mask); + so_data (so, nvgl_stencil_op(cso->stencil[0].fail_op)); + so_data (so, nvgl_stencil_op(cso->stencil[0].zfail_op)); + so_data (so, nvgl_stencil_op(cso->stencil[0].zpass_op)); + } else { + so_method(so, nv40->curie, NV40TCL_STENCIL_FRONT_ENABLE, 1); + so_data (so, 0); + } - hw->alpha.enabled = cso->alpha.enabled ? 1 : 0; - hw->alpha.func = nvgl_comparison_op(cso->alpha.func); - hw->alpha.ref = float_to_ubyte(cso->alpha.ref); + if (cso->stencil[1].enabled) { + so_method(so, nv40->curie, NV40TCL_STENCIL_BACK_ENABLE, 8); + so_data (so, cso->stencil[1].enabled ? 1 : 0); + so_data (so, cso->stencil[1].write_mask); + so_data (so, nvgl_comparison_op(cso->stencil[1].func)); + so_data (so, cso->stencil[1].ref_value); + so_data (so, cso->stencil[1].value_mask); + so_data (so, nvgl_stencil_op(cso->stencil[1].fail_op)); + so_data (so, nvgl_stencil_op(cso->stencil[1].zfail_op)); + so_data (so, nvgl_stencil_op(cso->stencil[1].zpass_op)); + } else { + so_method(so, nv40->curie, NV40TCL_STENCIL_BACK_ENABLE, 1); + so_data (so, 0); + } - return (void *)hw; + return (void *)so; } static void nv40_depth_stencil_alpha_state_bind(struct pipe_context *pipe, void *hwcso) { struct nv40_context *nv40 = nv40_context(pipe); - struct nv40_depth_stencil_alpha_state *hw = hwcso; - - BEGIN_RING(curie, NV40TCL_DEPTH_FUNC, 3); - OUT_RINGp ((uint32_t *)&hw->depth, 3); - BEGIN_RING(curie, NV40TCL_STENCIL_FRONT_ENABLE, 16); - OUT_RINGp ((uint32_t *)&hw->stencil.front, 8); - OUT_RINGp ((uint32_t *)&hw->stencil.back, 8); - BEGIN_RING(curie, NV40TCL_ALPHA_TEST_ENABLE, 3); - OUT_RINGp ((uint32_t *)&hw->alpha.enabled, 3); + + so_emit(nv40->nvws, hwcso); } static void nv40_depth_stencil_alpha_state_delete(struct pipe_context *pipe, void *hwcso) { - free(hwcso); + struct nouveau_stateobj *so = hwcso; + + so_ref(NULL, &so); } static void * @@ -502,12 +500,16 @@ nv40_set_blend_color(struct pipe_context *pipe, const struct pipe_blend_color *bcol) { struct nv40_context *nv40 = nv40_context(pipe); + struct nouveau_stateobj *so = so_new(2, 0); + + so_method(so, nv40->curie, NV40TCL_BLEND_COLOR, 1); + so_data (so, ((float_to_ubyte(bcol->color[3]) << 24) | + (float_to_ubyte(bcol->color[0]) << 16) | + (float_to_ubyte(bcol->color[1]) << 8) | + (float_to_ubyte(bcol->color[2]) << 0))); - BEGIN_RING(curie, NV40TCL_BLEND_COLOR, 1); - OUT_RING ((float_to_ubyte(bcol->color[3]) << 24) | - (float_to_ubyte(bcol->color[0]) << 16) | - (float_to_ubyte(bcol->color[1]) << 8) | - (float_to_ubyte(bcol->color[2]) << 0)); + so_emit(nv40->nvws, so); + so_ref(NULL, &so); } static void @@ -540,6 +542,8 @@ nv40_set_framebuffer_state(struct pipe_context *pipe, struct pipe_surface *rt[4], *zeta; uint32_t rt_enable, rt_format, w, h; int i, colour_format = 0, zeta_format = 0; + struct nouveau_stateobj *so = so_new(64, 10); + unsigned rt_flags = NOUVEAU_BO_RDWR | NOUVEAU_BO_VRAM; rt_enable = 0; for (i = 0; i < 4; i++) { @@ -603,66 +607,78 @@ nv40_set_framebuffer_state(struct pipe_context *pipe, } if (rt_enable & NV40TCL_RT_ENABLE_COLOR0) { - nv40->rt[0] = rt[0]->buffer; - BEGIN_RING(curie, NV40TCL_DMA_COLOR0, 1); - OUT_RELOCo(nv40->rt[0], NOUVEAU_BO_VRAM | NOUVEAU_BO_WR); - BEGIN_RING(curie, NV40TCL_COLOR0_PITCH, 2); - OUT_RING (rt[0]->pitch * rt[0]->cpp); - OUT_RELOCl(nv40->rt[0], 0, NOUVEAU_BO_VRAM | NOUVEAU_BO_WR); + so_method(so, nv40->curie, NV40TCL_DMA_COLOR0, 1); + so_reloc (so, rt[0]->buffer, 0, rt_flags | NOUVEAU_BO_OR, + nv40->nvws->channel->vram->handle, + nv40->nvws->channel->gart->handle); + so_method(so, nv40->curie, NV40TCL_COLOR0_PITCH, 2); + so_data (so, rt[0]->pitch * rt[0]->cpp); + so_reloc (so, rt[0]->buffer, rt[0]->offset, rt_flags | + NOUVEAU_BO_LOW, 0, 0); } if (rt_enable & NV40TCL_RT_ENABLE_COLOR1) { - nv40->rt[1] = rt[1]->buffer; - BEGIN_RING(curie, NV40TCL_DMA_COLOR1, 1); - OUT_RELOCo(nv40->rt[1], NOUVEAU_BO_VRAM | NOUVEAU_BO_WR); - BEGIN_RING(curie, NV40TCL_COLOR1_OFFSET, 2); - OUT_RELOCl(nv40->rt[1], 0, NOUVEAU_BO_VRAM | NOUVEAU_BO_WR); - OUT_RING (rt[1]->pitch * rt[1]->cpp); + so_method(so, nv40->curie, NV40TCL_DMA_COLOR1, 1); + so_reloc (so, rt[1]->buffer, 0, rt_flags | NOUVEAU_BO_OR, + nv40->nvws->channel->vram->handle, + nv40->nvws->channel->gart->handle); + so_method(so, nv40->curie, NV40TCL_COLOR1_OFFSET, 2); + so_reloc (so, rt[1]->buffer, rt[1]->offset, rt_flags | + NOUVEAU_BO_LOW, 0, 0); + so_data (so, rt[1]->pitch * rt[1]->cpp); } if (rt_enable & NV40TCL_RT_ENABLE_COLOR2) { - nv40->rt[2] = rt[2]->buffer; - BEGIN_RING(curie, NV40TCL_DMA_COLOR2, 1); - OUT_RELOCo(nv40->rt[2], NOUVEAU_BO_VRAM | NOUVEAU_BO_WR); - BEGIN_RING(curie, NV40TCL_COLOR2_OFFSET, 1); - OUT_RELOCl(nv40->rt[2], 0, NOUVEAU_BO_VRAM | NOUVEAU_BO_WR); - BEGIN_RING(curie, NV40TCL_COLOR2_PITCH, 1); - OUT_RING (rt[2]->pitch * rt[2]->cpp); + so_method(so, nv40->curie, NV40TCL_DMA_COLOR2, 1); + so_reloc (so, rt[2]->buffer, 0, rt_flags | NOUVEAU_BO_OR, + nv40->nvws->channel->vram->handle, + nv40->nvws->channel->gart->handle); + so_method(so, nv40->curie, NV40TCL_COLOR2_OFFSET, 1); + so_reloc (so, rt[2]->buffer, rt[2]->offset, rt_flags | + NOUVEAU_BO_LOW, 0, 0); + so_method(so, nv40->curie, NV40TCL_COLOR2_PITCH, 1); + so_data (so, rt[2]->pitch * rt[2]->cpp); } if (rt_enable & NV40TCL_RT_ENABLE_COLOR3) { - nv40->rt[3] = rt[3]->buffer; - BEGIN_RING(curie, NV40TCL_DMA_COLOR3, 1); - OUT_RELOCo(nv40->rt[3], NOUVEAU_BO_VRAM | NOUVEAU_BO_WR); - BEGIN_RING(curie, NV40TCL_COLOR3_OFFSET, 1); - OUT_RELOCl(nv40->rt[3], 0, NOUVEAU_BO_VRAM | NOUVEAU_BO_WR); - BEGIN_RING(curie, NV40TCL_COLOR3_PITCH, 1); - OUT_RING (rt[3]->pitch * rt[3]->cpp); + so_method(so, nv40->curie, NV40TCL_DMA_COLOR3, 1); + so_reloc (so, rt[3]->buffer, 0, rt_flags | NOUVEAU_BO_OR, + nv40->nvws->channel->vram->handle, + nv40->nvws->channel->gart->handle); + so_method(so, nv40->curie, NV40TCL_COLOR3_OFFSET, 1); + so_reloc (so, rt[3]->buffer, rt[3]->offset, rt_flags | + NOUVEAU_BO_LOW, 0, 0); + so_method(so, nv40->curie, NV40TCL_COLOR3_PITCH, 1); + so_data (so, rt[3]->pitch * rt[3]->cpp); } if (zeta_format) { - nv40->zeta = zeta->buffer; - BEGIN_RING(curie, NV40TCL_DMA_ZETA, 1); - OUT_RELOCo(nv40->zeta, NOUVEAU_BO_VRAM | NOUVEAU_BO_WR); - BEGIN_RING(curie, NV40TCL_ZETA_OFFSET, 1); - OUT_RELOCl(nv40->zeta, 0, NOUVEAU_BO_VRAM | NOUVEAU_BO_WR); - BEGIN_RING(curie, NV40TCL_ZETA_PITCH, 1); - OUT_RING (zeta->pitch * zeta->cpp); + so_method(so, nv40->curie, NV40TCL_DMA_ZETA, 1); + so_reloc (so, zeta->buffer, 0, rt_flags | NOUVEAU_BO_OR, + nv40->nvws->channel->vram->handle, + nv40->nvws->channel->gart->handle); + so_method(so, nv40->curie, NV40TCL_ZETA_OFFSET, 1); + so_reloc (so, zeta->buffer, zeta->offset, rt_flags | + NOUVEAU_BO_LOW, 0, 0); + so_method(so, nv40->curie, NV40TCL_ZETA_PITCH, 1); + so_data (so, zeta->pitch * zeta->cpp); } - nv40->rt_enable = rt_enable; - BEGIN_RING(curie, NV40TCL_RT_ENABLE, 1); - OUT_RING (rt_enable); - BEGIN_RING(curie, NV40TCL_RT_HORIZ, 3); - OUT_RING ((w << 16) | 0); - OUT_RING ((h << 16) | 0); - OUT_RING (rt_format); - BEGIN_RING(curie, NV40TCL_VIEWPORT_HORIZ, 2); - OUT_RING ((w << 16) | 0); - OUT_RING ((h << 16) | 0); - BEGIN_RING(curie, NV40TCL_VIEWPORT_CLIP_HORIZ(0), 2); - OUT_RING (((w - 1) << 16) | 0); - OUT_RING (((h - 1) << 16) | 0); + so_method(so, nv40->curie, NV40TCL_RT_ENABLE, 1); + so_data (so, rt_enable); + so_method(so, nv40->curie, NV40TCL_RT_HORIZ, 3); + so_data (so, (w << 16) | 0); + so_data (so, (h << 16) | 0); + so_data (so, rt_format); + so_method(so, nv40->curie, NV40TCL_VIEWPORT_HORIZ, 2); + so_data (so, (w << 16) | 0); + so_data (so, (h << 16) | 0); + so_method(so, nv40->curie, NV40TCL_VIEWPORT_CLIP_HORIZ(0), 2); + so_data (so, ((w - 1) << 16) | 0); + so_data (so, ((h - 1) << 16) | 0); + + so_emit(nv40->nvws, so); + so_ref (so, &nv40->so_framebuffer); } static void @@ -670,9 +686,15 @@ nv40_set_polygon_stipple(struct pipe_context *pipe, const struct pipe_poly_stipple *stipple) { struct nv40_context *nv40 = nv40_context(pipe); + struct nouveau_stateobj *so = so_new(33, 0); + unsigned i; - BEGIN_RING(curie, NV40TCL_POLYGON_STIPPLE_PATTERN(0), 32); - OUT_RINGp ((uint32_t *)stipple->stipple, 32); + so_method(so, nv40->curie, NV40TCL_POLYGON_STIPPLE_PATTERN(0), 32); + for (i = 0; i < 32; i++) + so_data(so, stipple->stipple[i]); + + so_emit(nv40->nvws, so); + so_ref(NULL, &so); } static void @@ -680,10 +702,14 @@ nv40_set_scissor_state(struct pipe_context *pipe, const struct pipe_scissor_state *s) { struct nv40_context *nv40 = nv40_context(pipe); + struct nouveau_stateobj *so = so_new(3, 0); + + so_method(so, nv40->curie, NV40TCL_SCISSOR_HORIZ, 2); + so_data (so, ((s->maxx - s->minx) << 16) | s->minx); + so_data (so, ((s->maxy - s->miny) << 16) | s->miny); - BEGIN_RING(curie, NV40TCL_SCISSOR_HORIZ, 2); - OUT_RING (((s->maxx - s->minx) << 16) | s->minx); - OUT_RING (((s->maxy - s->miny) << 16) | s->miny); + so_emit(nv40->nvws, so); + so_ref(NULL, &so); } static void @@ -691,16 +717,20 @@ nv40_set_viewport_state(struct pipe_context *pipe, const struct pipe_viewport_state *vpt) { struct nv40_context *nv40 = nv40_context(pipe); - - BEGIN_RING(curie, NV40TCL_VIEWPORT_TRANSLATE_X, 8); - OUT_RINGf (vpt->translate[0]); - OUT_RINGf (vpt->translate[1]); - OUT_RINGf (vpt->translate[2]); - OUT_RINGf (vpt->translate[3]); - OUT_RINGf (vpt->scale[0]); - OUT_RINGf (vpt->scale[1]); - OUT_RINGf (vpt->scale[2]); - OUT_RINGf (vpt->scale[3]); + struct nouveau_stateobj *so = so_new(9, 0); + + so_method(so, nv40->curie, NV40TCL_VIEWPORT_TRANSLATE_X, 8); + so_data (so, fui(vpt->translate[0])); + so_data (so, fui(vpt->translate[1])); + so_data (so, fui(vpt->translate[2])); + so_data (so, fui(vpt->translate[3])); + so_data (so, fui(vpt->scale[0])); + so_data (so, fui(vpt->scale[1])); + so_data (so, fui(vpt->scale[2])); + so_data (so, fui(vpt->scale[3])); + + so_emit(nv40->nvws, so); + so_ref(NULL, &so); } static void diff --git a/src/mesa/pipe/nv40/nv40_state.h b/src/mesa/pipe/nv40/nv40_state.h index 24eea36db3a..e82ab9de98a 100644 --- a/src/mesa/pipe/nv40/nv40_state.h +++ b/src/mesa/pipe/nv40/nv40_state.h @@ -3,20 +3,6 @@ #include "pipe/p_state.h" -struct nv40_blend_state { - uint32_t b_enable; - uint32_t b_srcfunc; - uint32_t b_dstfunc; - uint32_t b_eqn; - - uint32_t l_enable; - uint32_t l_op; - - uint32_t c_mask; - - uint32_t d_enable; -}; - struct nv40_sampler_state { uint32_t fmt; uint32_t wrap; @@ -25,29 +11,6 @@ struct nv40_sampler_state { uint32_t bcol; }; -struct nv40_rasterizer_state { - uint32_t shade_model; - - uint32_t line_width; - uint32_t line_smooth_en; - uint32_t line_stipple_en; - uint32_t line_stipple; - - uint32_t point_size; - - uint32_t poly_smooth_en; - uint32_t poly_stipple_en; - - uint32_t poly_mode_front; - uint32_t poly_mode_back; - - uint32_t front_face; - uint32_t cull_face; - uint32_t cull_face_en; - - uint32_t point_sprite; -}; - struct nv40_vertex_program_exec { uint32_t data[4]; boolean has_branch_offset; @@ -99,36 +62,7 @@ struct nv40_fragment_program { struct pipe_buffer *buffer; uint32_t fp_control; -}; - -struct nv40_stencil_push { - uint32_t enable; - uint32_t wmask; - uint32_t func; - uint32_t ref; - uint32_t vmask; - uint32_t fail; - uint32_t zfail; - uint32_t zpass; -}; - -struct nv40_depth_stencil_alpha_state { - struct { - uint32_t func; - uint32_t write_enable; - uint32_t test_enable; - } depth; - - struct { - struct nv40_stencil_push back; - struct nv40_stencil_push front; - } stencil; - - struct { - uint32_t enabled; - uint32_t func; - uint32_t ref; - } alpha; + struct nouveau_stateobj *so; }; struct nv40_miptree { diff --git a/src/mesa/pipe/nv40/nv40_state_emit.c b/src/mesa/pipe/nv40/nv40_state_emit.c index 66b98d5fab3..3a22cd4bd56 100644 --- a/src/mesa/pipe/nv40/nv40_state_emit.c +++ b/src/mesa/pipe/nv40/nv40_state_emit.c @@ -11,77 +11,15 @@ static void nv40_state_emit_dummy_relocs(struct nv40_context *nv40) { - unsigned rt_flags, tx_flags, fp_flags; - int i; + unsigned i; - rt_flags = NOUVEAU_BO_VRAM | NOUVEAU_BO_RDWR | NOUVEAU_BO_DUMMY; - tx_flags = NOUVEAU_BO_VRAM | NOUVEAU_BO_GART | NOUVEAU_BO_RD | - NOUVEAU_BO_DUMMY; - fp_flags = NOUVEAU_BO_VRAM | NOUVEAU_BO_GART | NOUVEAU_BO_RD | - NOUVEAU_BO_DUMMY; - - /* Render targets */ - if (nv40->rt_enable & NV40TCL_RT_ENABLE_COLOR0) { - OUT_RELOCm(nv40->rt[0], rt_flags, - curie, NV40TCL_DMA_COLOR0, 1); - OUT_RELOCo(nv40->rt[0], rt_flags); - OUT_RELOCm(nv40->rt[0], rt_flags, - curie, NV40TCL_COLOR0_OFFSET, 1); - OUT_RELOCl(nv40->rt[0], 0, rt_flags); - } - - if (nv40->rt_enable & NV40TCL_RT_ENABLE_COLOR1) { - OUT_RELOCm(nv40->rt[1], rt_flags, - curie, NV40TCL_DMA_COLOR1, 1); - OUT_RELOCo(nv40->rt[1], rt_flags); - OUT_RELOCm(nv40->rt[1], rt_flags, - curie, NV40TCL_COLOR1_OFFSET, 1); - OUT_RELOCl(nv40->rt[1], 0, rt_flags); - } - - if (nv40->rt_enable & NV40TCL_RT_ENABLE_COLOR2) { - OUT_RELOCm(nv40->rt[2], rt_flags, - curie, NV40TCL_DMA_COLOR2, 1); - OUT_RELOCo(nv40->rt[2], rt_flags); - OUT_RELOCm(nv40->rt[2], rt_flags, - curie, NV40TCL_COLOR2_OFFSET, 1); - OUT_RELOCl(nv40->rt[2], 0, rt_flags); - } - - if (nv40->rt_enable & NV40TCL_RT_ENABLE_COLOR3) { - OUT_RELOCm(nv40->rt[3], rt_flags, - curie, NV40TCL_DMA_COLOR3, 1); - OUT_RELOCo(nv40->rt[3], rt_flags); - OUT_RELOCm(nv40->rt[3], rt_flags, - curie, NV40TCL_COLOR3_OFFSET, 1); - OUT_RELOCl(nv40->rt[3], 0, rt_flags); - } - - if (nv40->zeta) { - OUT_RELOCm(nv40->zeta, rt_flags, curie, NV40TCL_DMA_ZETA, 1); - OUT_RELOCo(nv40->zeta, rt_flags); - OUT_RELOCm(nv40->zeta, rt_flags, curie, NV40TCL_ZETA_OFFSET, 1); - OUT_RELOCl(nv40->zeta, 0, rt_flags); - } - - /* Texture images */ + so_emit_reloc_markers(nv40->nvws, nv40->so_framebuffer); for (i = 0; i < 16; i++) { if (!(nv40->fp_samplers & (1 << i))) continue; - OUT_RELOCm(nv40->tex[i].buffer, tx_flags, - curie, NV40TCL_TEX_OFFSET(i), 2); - OUT_RELOCl(nv40->tex[i].buffer, 0, tx_flags); - OUT_RELOCd(nv40->tex[i].buffer, nv40->tex[i].format, - tx_flags | NOUVEAU_BO_OR, NV40TCL_TEX_FORMAT_DMA0, - NV40TCL_TEX_FORMAT_DMA1); + so_emit_reloc_markers(nv40->nvws, nv40->so_fragtex[i]); } - - /* Fragment program */ - OUT_RELOCm(nv40->fragprog.active->buffer, fp_flags, - curie, NV40TCL_FP_ADDRESS, 1); - OUT_RELOC (nv40->fragprog.active->buffer, 0, - fp_flags | NOUVEAU_BO_OR | NOUVEAU_BO_LOW, - NV40TCL_FP_ADDRESS_DMA0, NV40TCL_FP_ADDRESS_DMA1); + so_emit_reloc_markers(nv40->nvws, nv40->fragprog.active->so); } void diff --git a/src/mesa/pipe/nv40/nv40_vbo.c b/src/mesa/pipe/nv40/nv40_vbo.c index 0bb54c7610e..e2cb3fda8f2 100644 --- a/src/mesa/pipe/nv40/nv40_vbo.c +++ b/src/mesa/pipe/nv40/nv40_vbo.c @@ -97,13 +97,13 @@ nv40_vbo_static_attrib(struct nv40_context *nv40, int attrib, } static void -nv40_vbo_arrays_update(struct nv40_context *nv40) +nv40_vbo_arrays_update(struct nv40_context *nv40, struct pipe_buffer *ib, + unsigned ib_format) { struct nv40_vertex_program *vp = nv40->vertprog.active; - uint32_t inputs, vtxfmt[16]; - int hw, num_hw; - - nv40->vb_enable = 0; + struct nouveau_stateobj *vtxbuf, *vtxfmt; + unsigned inputs, hw, num_hw; + unsigned vb_flags = NOUVEAU_BO_VRAM | NOUVEAU_BO_GART | NOUVEAU_BO_RD; inputs = vp->ir; for (hw = 0; hw < 16 && inputs; hw++) { @@ -114,73 +114,64 @@ nv40_vbo_arrays_update(struct nv40_context *nv40) } num_hw++; + vtxbuf = so_new(20, 18); + so_method(vtxbuf, nv40->curie, NV40TCL_VTXBUF_ADDRESS(0), num_hw); + vtxfmt = so_new(17, 0); + so_method(vtxfmt, nv40->curie, NV40TCL_VTXFMT(0), num_hw); + inputs = vp->ir; for (hw = 0; hw < num_hw; hw++) { struct pipe_vertex_element *ve; struct pipe_vertex_buffer *vb; if (!(inputs & (1 << hw))) { - vtxfmt[hw] = NV40TCL_VTXFMT_TYPE_FLOAT; + so_data(vtxbuf, 0); + so_data(vtxfmt, NV40TCL_VTXFMT_TYPE_FLOAT); continue; } ve = &nv40->vtxelt[hw]; vb = &nv40->vtxbuf[ve->vertex_buffer_index]; - if (vb->pitch == 0) { - vtxfmt[hw] = NV40TCL_VTXFMT_TYPE_FLOAT; - if (nv40_vbo_static_attrib(nv40, hw, ve, vb) == TRUE) - continue; + if (!vb->pitch && nv40_vbo_static_attrib(nv40, hw, ve, vb)) { + so_data(vtxbuf, 0); + so_data(vtxfmt, NV40TCL_VTXFMT_TYPE_FLOAT); + continue; } - nv40->vb_enable |= (1 << hw); - nv40->vb[hw].delta = vb->buffer_offset + ve->src_offset; - nv40->vb[hw].buffer = vb->buffer; + so_reloc(vtxbuf, vb->buffer, vb->buffer_offset + ve->src_offset, + vb_flags | NOUVEAU_BO_LOW | NOUVEAU_BO_OR, + 0, NV40TCL_VTXBUF_ADDRESS_DMA1); + so_data (vtxfmt, ((vb->pitch << NV40TCL_VTXFMT_STRIDE_SHIFT) | + (nv40_vbo_ncomp(ve->src_format) << + NV40TCL_VTXFMT_SIZE_SHIFT) | + nv40_vbo_type(ve->src_format))); + } - vtxfmt[hw] = ((vb->pitch << NV40TCL_VTXFMT_STRIDE_SHIFT) | - (nv40_vbo_ncomp(ve->src_format) << - NV40TCL_VTXFMT_SIZE_SHIFT) | - nv40_vbo_type(ve->src_format)); + if (ib) { + so_method(vtxbuf, nv40->curie, NV40TCL_IDXBUF_ADDRESS, 2); + so_reloc (vtxbuf, ib, 0, vb_flags | NOUVEAU_BO_LOW, 0, 0); + so_reloc (vtxbuf, ib, ib_format, vb_flags | NOUVEAU_BO_OR, + 0, NV40TCL_IDXBUF_FORMAT_DMA1); } - BEGIN_RING(curie, NV40TCL_VTXFMT(0), num_hw); - OUT_RINGp (vtxfmt, num_hw); + so_emit(nv40->nvws, vtxfmt); + so_emit(nv40->nvws, vtxbuf); + so_ref (vtxbuf, &nv40->so_vtxbuf); + so_ref (NULL, &vtxfmt); } static boolean nv40_vbo_validate_state(struct nv40_context *nv40, struct pipe_buffer *ib, unsigned ib_format) { - unsigned inputs; - nv40_emit_hw_state(nv40); - - if (nv40->dirty & NV40_NEW_ARRAYS) { - nv40_vbo_arrays_update(nv40); + if (nv40->dirty & NV40_NEW_ARRAYS || ib) { + nv40_vbo_arrays_update(nv40, ib, ib_format); nv40->dirty &= ~NV40_NEW_ARRAYS; } - inputs = nv40->vb_enable; - while (inputs) { - unsigned a = ffs(inputs) - 1; - - inputs &= ~(1 << a); - - BEGIN_RING(curie, NV40TCL_VTXBUF_ADDRESS(a), 1); - OUT_RELOC (nv40->vb[a].buffer, nv40->vb[a].delta, - NOUVEAU_BO_VRAM | NOUVEAU_BO_GART | NOUVEAU_BO_LOW | - NOUVEAU_BO_OR | NOUVEAU_BO_RD, 0, - NV40TCL_VTXBUF_ADDRESS_DMA1); - } - - if (ib) { - BEGIN_RING(curie, NV40TCL_IDXBUF_ADDRESS, 2); - OUT_RELOCl(ib, 0, NOUVEAU_BO_VRAM | NOUVEAU_BO_GART | - NOUVEAU_BO_RD); - OUT_RELOCd(ib, ib_format, NOUVEAU_BO_VRAM | NOUVEAU_BO_GART | - NOUVEAU_BO_RD | NOUVEAU_BO_OR, - 0, NV40TCL_IDXBUF_FORMAT_DMA1); - } + so_emit_reloc_markers(nv40->nvws, nv40->so_vtxbuf); BEGIN_RING(curie, 0x1710, 1); OUT_RING (0); /* vtx cache flush */ -- 2.30.2