From e92a457ac0030e48f5260dc2ac00ca283be7d7ad Mon Sep 17 00:00:00 2001 From: Gary Wong Date: Tue, 28 Oct 2008 15:03:14 -0400 Subject: [PATCH] i965: Allocate temporaries contiguously with other regs in fragment shaders. This is required for threads to be spawned with correctly sized GRF register blocks. --- src/mesa/drivers/dri/i965/brw_wm.h | 2 ++ src/mesa/drivers/dri/i965/brw_wm_glsl.c | 8 +++++--- 2 files changed, 7 insertions(+), 3 deletions(-) diff --git a/src/mesa/drivers/dri/i965/brw_wm.h b/src/mesa/drivers/dri/i965/brw_wm.h index 297617ee2dc..b39b2714ecd 100644 --- a/src/mesa/drivers/dri/i965/brw_wm.h +++ b/src/mesa/drivers/dri/i965/brw_wm.h @@ -246,7 +246,9 @@ struct brw_wm_compile { struct brw_reg stack; struct brw_reg emit_mask_reg; GLuint reg_index; + GLuint tmp_regs[BRW_WM_MAX_GRF]; GLuint tmp_index; + GLuint tmp_max; }; diff --git a/src/mesa/drivers/dri/i965/brw_wm_glsl.c b/src/mesa/drivers/dri/i965/brw_wm_glsl.c index 4d5e11f4b6f..b8a6b7b2339 100644 --- a/src/mesa/drivers/dri/i965/brw_wm_glsl.c +++ b/src/mesa/drivers/dri/i965/brw_wm_glsl.c @@ -47,13 +47,16 @@ static int get_scalar_dst_index(struct prog_instruction *inst) static struct brw_reg alloc_tmp(struct brw_wm_compile *c) { struct brw_reg reg; - reg = brw_vec8_grf(c->tmp_index--, 0); + if(c->tmp_index == c->tmp_max) + c->tmp_regs[ c->tmp_max++ ] = c->reg_index++; + + reg = brw_vec8_grf(c->tmp_regs[ c->tmp_index++ ], 0); return reg; } static void release_tmps(struct brw_wm_compile *c) { - c->tmp_index = 127; + c->tmp_index = 0; } static struct brw_reg @@ -1368,7 +1371,6 @@ static void brw_wm_emit_glsl(struct brw_context *brw, struct brw_wm_compile *c) void brw_wm_glsl_emit(struct brw_context *brw, struct brw_wm_compile *c) { brw_wm_pass_fp(c); - c->tmp_index = 127; brw_wm_emit_glsl(brw, c); c->prog_data.total_grf = c->reg_index; c->prog_data.total_scratch = 0; -- 2.30.2