From e941f8bd7f3318419f417ab3cfb4b16cb6a8da52 Mon Sep 17 00:00:00 2001 From: lkcl Date: Mon, 9 May 2022 05:01:51 +0100 Subject: [PATCH] --- openpower/sv/SimpleV_rationale.mdwn | 10 ++++++---- 1 file changed, 6 insertions(+), 4 deletions(-) diff --git a/openpower/sv/SimpleV_rationale.mdwn b/openpower/sv/SimpleV_rationale.mdwn index eb59d1ecd..9fb2c9010 100644 --- a/openpower/sv/SimpleV_rationale.mdwn +++ b/openpower/sv/SimpleV_rationale.mdwn @@ -891,10 +891,11 @@ the computation. In this case, that's an expensive inconvenience (similar to the problems associated with Memory-to-Memory Vector Machines such as the CDC Star-100). -Vertical-First allows *scalar* temporary registers to be utilised +Vertical-First allows *scalar* instructions and +*scalar* temporary registers to be utilised in the assessment as to whether a particular Vector element should be skipped, utilising a straight Branch instruction *(or ZOLC -Conditions)*. This technique +Conditions)*. The Vertical Vector technique is pioneered by Mitch Alsup and is a key feature of his VVM Extension to MyISA 66000. Careful analysis of the registers within the Vertical-First Loop allows a Multi-Issue Out-of-Order Engine to @@ -906,10 +907,11 @@ in-flight Reservation Stations in the first place. (With thanks and gratitude to Mitch Alsup on comp.arch for spending considerable time explaining VVM, how its Loop Construct explicitly identifies loop-invariant registers, -and how that helps to exploit a GB-OoO Micro-architectures) +and how that helps Register Hazards and SIMD amortisation +on a GB-OoO Micro-architecture) * -**Use-case: More powerful in-memory PEs** +**Use-case variant: More powerful in-memory PEs** An obvious variant of the above is that, if there is inherently more parallelism in the data set, then the PEs get their own -- 2.30.2