From e950440861f7e8ae82be7677739e4fd0576318ad Mon Sep 17 00:00:00 2001 From: Luke Kenneth Casson Leighton Date: Thu, 18 Mar 2021 12:24:54 +0000 Subject: [PATCH] add sv_out2 to PowerDecode and PowerDecoder2 used for 2nd write (currently LD/ST update only) --- src/soc/decoder/power_decoder.py | 2 ++ src/soc/decoder/power_decoder2.py | 3 ++- 2 files changed, 4 insertions(+), 1 deletion(-) diff --git a/src/soc/decoder/power_decoder.py b/src/soc/decoder/power_decoder.py index 23954142..eb6df3cf 100644 --- a/src/soc/decoder/power_decoder.py +++ b/src/soc/decoder/power_decoder.py @@ -131,6 +131,7 @@ power_op_types = {'function_unit': Function, 'sv_in2': SVEXTRA, 'sv_in3': SVEXTRA, 'sv_out': SVEXTRA, + 'sv_out2': SVEXTRA, 'sv_cr_in': SVEXTRA, 'sv_cr_out': SVEXTRA, 'ldst_len': LdstLen, @@ -150,6 +151,7 @@ power_op_csvmap = {'function_unit': 'unit', 'sv_in2': 'sv_in2', 'sv_in3': 'sv_in3', 'sv_out': 'sv_out', + 'sv_out2': 'sv_out2', 'sv_cr_in': 'sv_cr_in', 'sv_cr_out': 'sv_cr_out', 'SV_Etype': 'SV_Etype', diff --git a/src/soc/decoder/power_decoder2.py b/src/soc/decoder/power_decoder2.py index 3813295c..abed03ec 100644 --- a/src/soc/decoder/power_decoder2.py +++ b/src/soc/decoder/power_decoder2.py @@ -944,6 +944,7 @@ class PowerDecode2(PowerDecodeSubset): subset.add("sv_in2") subset.add("sv_in3") subset.add("sv_out") + subset.add("sv_out2") subset.add("sv_cr_in") subset.add("sv_cr_out") subset.add("SV_Etype") @@ -1083,10 +1084,10 @@ class PowerDecode2(PowerDecodeSubset): comb += in2_svdec.idx.eq(op.sv_in2) # SVP64 reg #2 (in2_sel) comb += in3_svdec.idx.eq(op.sv_in3) # SVP64 reg #3 (in3_sel) comb += o_svdec.idx.eq(op.sv_out) # SVP64 output (out_sel) + comb += o2_svdec.idx.eq(op.sv_out2) # SVP64 output (implicit) # XXX TODO - work out where this should come from. the problem is # that LD-with-update is implied (computed from "is instruction in # "update mode" rather than specified cleanly as its own CSV column - #comb += o2_svdec.idx.eq(op.sv_out) # SVP64 output (implicit) # output reg-is-vectorised (and when no in/out is vectorised) comb += self.in1_isvec.eq(in1_svdec.isvec) -- 2.30.2