From e96dd32b05c1390708539af2cc24c6236f86c7f6 Mon Sep 17 00:00:00 2001 From: Luke Kenneth Casson Leighton Date: Sun, 22 Jul 2018 07:11:30 +0100 Subject: [PATCH] tidyup output --- src/bsv/bsv_lib/slow_peripherals_template.bsv | 88 ++++++++++--------- src/bsv/peripheral_gen.py | 28 +++--- 2 files changed, 61 insertions(+), 55 deletions(-) diff --git a/src/bsv/bsv_lib/slow_peripherals_template.bsv b/src/bsv/bsv_lib/slow_peripherals_template.bsv index 57abf41..76164a3 100644 --- a/src/bsv/bsv_lib/slow_peripherals_template.bsv +++ b/src/bsv/bsv_lib/slow_peripherals_template.bsv @@ -57,29 +57,31 @@ package slow_peripherals; `endif `ifdef PLIC method ActionValue#(Tuple2#(Bool,Bool)) intrpt_note; `endif interface IOCellSide iocell_side; // mandatory interface + `ifdef PLIC {1} + `endif endinterface /*================================*/ function Tuple2#(Bool, Bit#(TLog#(Num_Slow_Slaves))) fn_address_mapping (Bit#(`ADDR) addr); - `ifdef CLINT - if(addr>=`ClintBase && addr<=`ClintEnd) - return tuple2(True,fromInteger(valueOf(CLINT_slave_num))); - else - `endif - `ifdef PLIC - if(addr>=`PLICBase && addr<=`PLICEnd) - return tuple2(True,fromInteger(valueOf(Plic_slave_num))); - else - `endif - `ifdef AXIEXP - if(addr>=`AxiExp1Base && addr<=`AxiExp1End) - return tuple2(True,fromInteger(valueOf(AxiExp1_slave_num))); - else - `endif + `ifdef CLINT + if(addr>=`ClintBase && addr<=`ClintEnd) + return tuple2(True,fromInteger(valueOf(CLINT_slave_num))); + else + `endif + `ifdef PLIC + if(addr>=`PLICBase && addr<=`PLICEnd) + return tuple2(True,fromInteger(valueOf(Plic_slave_num))); + else + `endif + `ifdef AXIEXP + if(addr>=`AxiExp1Base && addr<=`AxiExp1End) + return tuple2(True,fromInteger(valueOf(AxiExp1_slave_num))); + else + `endif {4} - return tuple2(False,?); + return tuple2(False,?); endfunction (*synthesize*) @@ -93,23 +95,25 @@ package slow_peripherals; /*======= Module declarations for each peripheral =======*/ {5} `ifdef CLINT - Ifc_clint clint <- mkclint(); + Ifc_clint clint <- mkclint(); `endif `ifdef PLIC - Ifc_PLIC_AXI plic <- mkplicperipheral(); - Wire#(Bit#(TLog#(`INTERRUPT_PINS))) interrupt_id <- mkWire(); - Vector#(`INTERRUPT_PINS, FIFO#(bit)) ff_gateway_queue <- replicateM(mkFIFO); + Ifc_PLIC_AXI plic <- mkplicperipheral(); + Wire#(Bit#(TLog#(`INTERRUPT_PINS))) interrupt_id <- mkWire(); + Vector#(`INTERRUPT_PINS, FIFO#(bit)) + ff_gateway_queue <- replicateM(mkFIFO); `endif `ifdef AXIEXP - Ifc_AxiExpansion axiexp1 <- mkAxiExpansion(); + Ifc_AxiExpansion axiexp1 <- mkAxiExpansion(); `endif - Ifc_pinmux pinmux <- mkpinmux; // mandatory + Ifc_pinmux pinmux <- mkpinmux; // mandatory + /*=======================================================*/ - AXI4_Lite_Fabric_IFC #(1, Num_Slow_Slaves, `ADDR, `DATA,`USERSPACE) - slow_fabric <- mkAXI4_Lite_Fabric(fn_address_mapping); + AXI4_Lite_Fabric_IFC #(1, Num_Slow_Slaves, `ADDR, `DATA,`USERSPACE) + slow_fabric <- mkAXI4_Lite_Fabric(fn_address_mapping); Ifc_AXI4Lite_AXI4_Bridge - bridge<-mkAXI4Lite_AXI4_Bridge(fast_clock,fast_reset); + bridge<-mkAXI4Lite_AXI4_Bridge(fast_clock,fast_reset); mkConnection (bridge.axi4_lite_master, slow_fabric.v_from_masters [0]); /*======= Slave connections to AXI4Lite fabric =========*/ @@ -135,6 +139,7 @@ package slow_peripherals; {8} /*=================== PLIC Connections ==================== */ +`ifdef PLIC {10} rule rl_completion_msg_from_plic; @@ -155,24 +160,21 @@ package slow_peripherals; end endrule end - `ifdef PLIC_main - /*TODO DMA interrupt need to be connected to the plic */ - for(Integer i=1; i<8; i=i+1) begin - `ifdef DMA - rule rl_connect_dma_interrupts_to_plic; - if(dma.interrupt_to_processor[i-1]==1'b1) begin - ff_gateway_queue[i].enq(1); - plic.ifc_external_irq[i].irq_frm_gateway(True); - end - endrule - `else - rule rl_connect_dma_interrupts_to_plic; - ff_gateway_queue[i].enq(0); - endrule - `endif - end + /*TODO DMA interrupt need to be connected to the plic */ + for(Integer i=1; i<8; i=i+1) begin + rule rl_connect_dma_interrupts_to_plic; + `ifdef DMA + if(dma.interrupt_to_processor[i-1]==1'b1) begin + ff_gateway_queue[i].enq(1); + plic.ifc_external_irq[i].irq_frm_gateway(True); + end + `else + ff_gateway_queue[i].enq(0); + `endif + endrule + end - `endif +`endif /*======================================================= */ /* ===== interface definition =======*/ @@ -183,7 +185,9 @@ package slow_peripherals; method mtip_int=clint.mtip_int; method mtime=clint.mtime; `endif +`ifdef PLIC {12} +`endif interface SP_dedicated_ios slow_ios; /* template for dedicated peripherals `ifdef UART0 diff --git a/src/bsv/peripheral_gen.py b/src/bsv/peripheral_gen.py index aa09b0b..5d2d98a 100644 --- a/src/bsv/peripheral_gen.py +++ b/src/bsv/peripheral_gen.py @@ -196,8 +196,8 @@ mkplic_rule = """\ class uart(PBase): def slowimport(self): - return " import Uart_bs :: *;\n" + \ - " import RS232_modified::*;" + return " import Uart_bs :: *;\n" + \ + " import RS232_modified::*;" def slowifdecl(self): return " interface RS232 uart{0}_coe;\n" + \ @@ -224,7 +224,7 @@ class uart(PBase): class quart(PBase): def slowimport(self): - return " import Uart16550 :: *;" + return " import Uart16550 :: *;" def slowifdecl(self): return " interface RS232_PHY_Ifc quart{0}_coe;\n" + \ @@ -297,8 +297,8 @@ uart_plic_template = """\ class rs232(PBase): def slowimport(self): - return " import Uart_bs::*;\n" + \ - " import RS232_modified::*;" + return " import Uart_bs::*;\n" + \ + " import RS232_modified::*;" def slowifdecl(self): return " interface RS232 uart{0}_coe;" @@ -327,7 +327,7 @@ class rs232(PBase): class twi(PBase): def slowimport(self): - return " import I2C_top :: *;" + return " import I2C_top :: *;" def slowifdecl(self): return " interface I2C_out twi{0}_out;\n" + \ @@ -421,12 +421,14 @@ class eint(PBase): eint_pincon_template = '''\ // EINT is offset at end of other peripheral interrupts +`ifdef PLIC for(Integer i=0;i<{0};i=i+ 1)begin rule connect_int_to_plic(wr_interrupt[i]==1); ff_gateway_queue[i+`NUM_SLOW_IRQS].enq(1); plic.ifc_external_irq[i+`NUM_SLOW_IRQS].irq_frm_gateway(True); endrule end +`endif ''' @@ -466,7 +468,7 @@ jtag_method_template = """\ class sdmmc(PBase): def slowimport(self): - return " import sdcard_dummy :: *;" + return " import sdcard_dummy :: *;" def slowifdecl(self): return " interface QSPI_out sd{0}_out;\n" + \ @@ -497,7 +499,7 @@ class sdmmc(PBase): class spi(PBase): def slowimport(self): - return " import qspi :: *;" + return " import qspi :: *;" def slowifdecl(self): return " interface QSPI_out spi{0}_out;\n" + \ @@ -555,7 +557,7 @@ class spi(PBase): class qspi(PBase): def slowimport(self): - return " import qspi :: *;" + return " import qspi :: *;" def slowifdecl(self): return " interface QSPI_out qspi{0}_out;\n" + \ @@ -630,7 +632,7 @@ class qspi(PBase): class pwm(PBase): def slowimport(self): - return " import pwm::*;" + return " import pwm::*;" def slowifdecl(self): return " interface PWMIO pwm{0}_io;" @@ -651,9 +653,9 @@ class pwm(PBase): class gpio(PBase): def slowimport(self): - return " import pinmux::*;\n" + \ - " import mux::*;\n" + \ - " import gpio::*;\n" + return " import pinmux::*;\n" + \ + " import mux::*;\n" + \ + " import gpio::*;\n" def slowifdeclmux(self): size = len(self.peripheral.pinspecs) -- 2.30.2