From e9c35dd7cce5b09d8b89eaab8b79a4703b661f49 Mon Sep 17 00:00:00 2001 From: Sagar Ghuge Date: Tue, 4 Jun 2019 13:04:49 -0700 Subject: [PATCH] intel/tools: Add ROL/ROR support in assembler Signed-off-by: Sagar Ghuge Reviewed-by: Matt Turner --- src/intel/tools/i965_gram.y | 8 ++++++++ src/intel/tools/i965_lex.l | 2 ++ 2 files changed, 10 insertions(+) diff --git a/src/intel/tools/i965_gram.y b/src/intel/tools/i965_gram.y index bbe7ce53f6b..2b906a27503 100644 --- a/src/intel/tools/i965_gram.y +++ b/src/intel/tools/i965_gram.y @@ -189,6 +189,12 @@ i965_asm_binary_instruction(int opcode, case BRW_OPCODE_PLN: brw_PLN(p, dest, src0, src1); break; + case BRW_OPCODE_ROL: + brw_ROL(p, dest, src0, src1); + break; + case BRW_OPCODE_ROR: + brw_ROR(p, dest, src0, src1); + break; case BRW_OPCODE_SAD2: fprintf(stderr, "Opcode BRW_OPCODE_SAD2 unhandled\n"); break; @@ -720,6 +726,8 @@ binaryopcodes: | MACH | MUL | PLN + | ROL + | ROR | SAD2 | SADA2 | SUBB diff --git a/src/intel/tools/i965_lex.l b/src/intel/tools/i965_lex.l index 3aa2bd64083..3732c6c24c0 100644 --- a/src/intel/tools/i965_lex.l +++ b/src/intel/tools/i965_lex.l @@ -112,6 +112,8 @@ rndd { yylval.integer = BRW_OPCODE_RNDD; return RNDD; } rnde { yylval.integer = BRW_OPCODE_RNDE; return RNDE; } rndu { yylval.integer = BRW_OPCODE_RNDU; return RNDU; } rndz { yylval.integer = BRW_OPCODE_RNDZ; return RNDZ; } +rol { yylval.integer = BRW_OPCODE_ROL; return ROL; } +ror { yylval.integer = BRW_OPCODE_ROR; return ROR; } sad2 { yylval.integer = BRW_OPCODE_SAD2; return SAD2; } sada2 { yylval.integer = BRW_OPCODE_SADA2; return SADA2; } sel { yylval.integer = BRW_OPCODE_SEL; return SEL; } -- 2.30.2