From e9cf4def637bcd541c1c06444eda332c079608b8 Mon Sep 17 00:00:00 2001 From: Luke Kenneth Casson Leighton Date: Mon, 17 Jan 2022 17:59:59 +0000 Subject: [PATCH] connect up DEC/TB FSM pauser from core to Issuer --- src/soc/simple/issuer.py | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/src/soc/simple/issuer.py b/src/soc/simple/issuer.py index e11f3d35..ab21b1b9 100644 --- a/src/soc/simple/issuer.py +++ b/src/soc/simple/issuer.py @@ -396,6 +396,10 @@ class TestIssuerBase(Elaboratable): m.submodules["sram4k_%d" % i] = csd(sram) comb += sram.enable.eq(self.wb_sram_en) + # terrible hack to stop a potential race condition. if core + # is doing any operation (at all) pause the DEC/TB FSM + comb += self.pause_dec_tb.eq(core.pause_dec_tb) + # XICS interrupt handler if self.xics: m.submodules.xics_icp = icp = csd(self.xics_icp) -- 2.30.2