From e9d129ab0fd2c2ce9e5ce4a409bacbf1b0b3a81c Mon Sep 17 00:00:00 2001 From: Tim Newsome Date: Thu, 15 Jun 2017 12:58:40 -0700 Subject: [PATCH] Test 64-bit addressing. The spike64 target now links all test programs at 0x7fff_ffff_ffff_0000. Also a minor change to log file naming so that 'make all' works again. I'll fix this better later. --- debug/programs/infinite_loop | Bin 9288 -> 0 bytes debug/programs/infinite_loop.c | 13 +++---- debug/targets.py | 24 +++++++++---- debug/targets/{spike => spike32}/link.lds | 0 debug/targets/{spike => spike32}/openocd.cfg | 0 debug/targets/spike64/link.lds | 34 +++++++++++++++++++ debug/targets/spike64/openocd.cfg | 19 +++++++++++ debug/testlib.py | 29 +++++++++------- 8 files changed, 90 insertions(+), 29 deletions(-) delete mode 100755 debug/programs/infinite_loop rename debug/targets/{spike => spike32}/link.lds (100%) rename debug/targets/{spike => spike32}/openocd.cfg (100%) create mode 100755 debug/targets/spike64/link.lds create mode 100644 debug/targets/spike64/openocd.cfg diff --git a/debug/programs/infinite_loop b/debug/programs/infinite_loop deleted file mode 100755 index 0cf68cb1665b7552c9f5afee612d7e2449d3f6de..0000000000000000000000000000000000000000 GIT binary patch literal 0 HcmV?d00001 literal 9288 zcmeI2O-mb56o$`C;wL4<6jbcyDy8aXk`&b1g+xT-qDVKjAi_9K#%Abzgm{Iz(hB|$ zm#+O0{+&`v*Y@16WHOCVDCp)~m^tUZbKY}ro=i63UTlBZu`LVCu;CY|nN=2ALqFJE zP|1kY-eFAx#$im>j)_OIS|rM6BGbBw{W?)gg9s1-B0vO)01+SpM1Tko0U|&IhyW3I z3Ia1z052`e{sBi|-E2->H#hF@n%@_HKa6Z|T344(u?Jd%2oM1xKm>>Y5g-CYfCvx) zB0vO)01n%y&F68R^_%yrr2U4k zvE}_$?Jwv8^Bz8SZbht>9V<8yS}iML&X^MBa=P(nV}4J<(qPKi)`f!4Bwpi6hFKja jFq*w -#include -#include -#include - +volatile int forever = 1; int main() { + while (forever) + ; - volatile int forever = 1; - while (forever); - - return 1; + return 1; } diff --git a/debug/targets.py b/debug/targets.py index bd177ec..525561e 100644 --- a/debug/targets.py +++ b/debug/targets.py @@ -60,31 +60,41 @@ class Target(object): def extensionSupported(self, letter): # target.misa is set by testlib.ExamineTarget - return self.misa & (1 << (ord(letter.upper()) - ord('A'))) + if self.misa: + return self.misa & (1 << (ord(letter.upper()) - ord('A'))) + else: + return False class SpikeTarget(Target): # pylint: disable=abstract-method - directory = "spike" - ram = 0x10000000 - ram_size = 0x10000000 instruction_hardware_breakpoint_count = 4 reset_vector = 0x1000 - openocd_config = "targets/%s/openocd.cfg" % directory class Spike64Target(SpikeTarget): name = "spike64" + directory = name xlen = 64 use_fpu = True + # Would like to use 0x7fffffffffff0000 because it crosses the 0x8000... + # boundary, but spike doesn't support that in the code where it generates + # the reset vector. + ram = 0x1212340000 + ram_size = 0x10000000 + openocd_config = "targets/%s/openocd.cfg" % directory def target(self): - return testlib.Spike(self.sim_cmd) + return testlib.Spike(self) class Spike32Target(SpikeTarget): name = "spike32" + directory = name xlen = 32 + ram = 0x10000000 + ram_size = 0x10000000 + openocd_config = "targets/%s/openocd.cfg" % directory def target(self): - return testlib.Spike(self.sim_cmd, xlen=32) + return testlib.Spike(self) class FreedomE300Target(Target): name = "freedom-e300" diff --git a/debug/targets/spike/link.lds b/debug/targets/spike32/link.lds similarity index 100% rename from debug/targets/spike/link.lds rename to debug/targets/spike32/link.lds diff --git a/debug/targets/spike/openocd.cfg b/debug/targets/spike32/openocd.cfg similarity index 100% rename from debug/targets/spike/openocd.cfg rename to debug/targets/spike32/openocd.cfg diff --git a/debug/targets/spike64/link.lds b/debug/targets/spike64/link.lds new file mode 100755 index 0000000..dc7cb63 --- /dev/null +++ b/debug/targets/spike64/link.lds @@ -0,0 +1,34 @@ +OUTPUT_ARCH( "riscv" ) + +SECTIONS +{ + . = 0x1212340000; + .text : + { + *(.text.entry) + *(.text) + } + + /* data segment */ + .data : { *(.data) } + + .sdata : { + __global_pointer$ = . + 0x800; + *(.srodata.cst16) *(.srodata.cst8) *(.srodata.cst4) *(.srodata.cst2) + *(.srodata*) + *(.sdata .sdata.* .gnu.linkonce.s.*) + } + + /* bss segment */ + .sbss : { + *(.sbss .sbss.* .gnu.linkonce.sb.*) + *(.scommon) + } + .bss : { *(.bss) } + + __malloc_start = .; + . = . + 512; + + /* End of uninitalized data segement */ + _end = .; +} diff --git a/debug/targets/spike64/openocd.cfg b/debug/targets/spike64/openocd.cfg new file mode 100644 index 0000000..2742335 --- /dev/null +++ b/debug/targets/spike64/openocd.cfg @@ -0,0 +1,19 @@ +adapter_khz 10000 + +interface remote_bitbang +remote_bitbang_host $::env(REMOTE_BITBANG_HOST) +remote_bitbang_port $::env(REMOTE_BITBANG_PORT) + +set _CHIPNAME riscv +jtag newtap $_CHIPNAME cpu -irlen 5 -expected-id 0x10e31913 + +set _TARGETNAME $_CHIPNAME.cpu +#target create $_TARGETNAME riscv -chain-position $_TARGETNAME -rtos riscv +target create $_TARGETNAME riscv -chain-position $_TARGETNAME + +gdb_report_data_abort enable + +init +reset halt + +echo "Ready for Remote Connections" diff --git a/debug/testlib.py b/debug/testlib.py index 27bef1a..43b818e 100644 --- a/debug/testlib.py +++ b/debug/testlib.py @@ -55,35 +55,34 @@ def unused_port(): return port class Spike(object): - logname = "spike.log" + logname = "spike-%d.log" % os.getpid() - def __init__(self, sim_cmd, binary=None, halted=False, with_jtag_gdb=True, - timeout=None, xlen=64): + def __init__(self, target, halted=False, timeout=None, with_jtag_gdb=True): """Launch spike. Return tuple of its process and the port it's running on.""" - if sim_cmd: - cmd = shlex.split(sim_cmd) + if target.sim_cmd: + cmd = shlex.split(target.sim_cmd) else: spike = os.path.expandvars("$RISCV/bin/spike") cmd = [spike] - if xlen == 32: + if target.xlen == 32: cmd += ["--isa", "RV32G"] else: cmd += ["--isa", "RV64G"] + cmd += ["-m0x%x:0x%x" % (target.ram, target.ram_size)] if timeout: cmd = ["timeout", str(timeout)] + cmd - cmd += ["-m0x10000000:0x10000000"] - if halted: cmd.append('-H') if with_jtag_gdb: cmd += ['--rbb-port', '0'] os.environ['REMOTE_BITBANG_HOST'] = 'localhost' - cmd.append('programs/infinite_loop') - if binary: - cmd.append(binary) + self.infinite_loop = target.compile( + "programs/checksum.c", "programs/tiny-malloc.c", + "programs/infinite_loop.c", "-DDEFINE_MALLOC", "-DDEFINE_FREE") + cmd.append(self.infinite_loop) logfile = open(self.logname, "w") logfile.write("+ %s\n" % " ".join(cmd)) logfile.flush() @@ -155,7 +154,7 @@ class VcsSim(object): pass class Openocd(object): - logname = "openocd.log" + logname = "openocd-%d.log" % os.getpid() def __init__(self, server_cmd=None, config=None, debug=False): if server_cmd: @@ -212,6 +211,9 @@ class Openocd(object): if not messaged and time.time() - start > 1: messaged = True print "Waiting for OpenOCD to examine RISCV core..." + if time.time() - start > 60: + raise Exception("ERROR: Timed out waiting for OpenOCD to " + "examine RISCV core") self.port = self._get_gdb_server_port() @@ -577,7 +579,8 @@ class ExamineTarget(GdbTest): elif (self.target.misa >> 126) == 3: txt += "128" else: - txt += "??" + raise TestFailed("Couldn't determine XLEN from $misa (0x%x)" % + self.target.misa) for i in range(26): if self.target.misa & (1<