From e9df81766e83d80a9cc2879c4f5ad3db846af438 Mon Sep 17 00:00:00 2001 From: lkcl Date: Wed, 9 Aug 2023 22:38:36 +0100 Subject: [PATCH] --- 3d_gpu/architecture/inorder_model.mdwn | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/3d_gpu/architecture/inorder_model.mdwn b/3d_gpu/architecture/inorder_model.mdwn index a848c4e4e..112a823e3 100644 --- a/3d_gpu/architecture/inorder_model.mdwn +++ b/3d_gpu/architecture/inorder_model.mdwn @@ -14,11 +14,11 @@ instruction will take tens of clock cycles to complete. In-development (Andrey to research and link to the relevant bugreport) is an in-order core and following on from that will be an out-of-order core. -A Single-Issue In-Order control unit will allow every pipepline to be active, +A Single-Issue In-Order control unit (written 12+ months ago) will allow every pipepline to be active, and raises the ideal maximum throughput to 1 instruction per clock cycle, bearing any register hazards. -This control unit has not been written in HDL yet (incorrect: the first version was written 18 months ago, and is in soc/ and there are options in the Makefile to enable it), however there's currently a +This control unit has not been written in HDL yet (incorrect: the first version was written 12+ months ago, and is in soc/ and there are options in the Makefile to enable it), however there's currently a task to develop the model for the simulator first. The model will be used to determine performance. -- 2.30.2