From e9e30598e08e4f162b523f9ef07f1510f3cfe0a6 Mon Sep 17 00:00:00 2001
From: Andrew Waterman <andrew@sifive.com>
Date: Sat, 7 Jan 2017 18:03:16 -0800
Subject: [PATCH] Only allow SIP.SSIP to be toggled if the interrupt is
 delegated

---
 riscv/processor.cc | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/riscv/processor.cc b/riscv/processor.cc
index 75f4002..7417acf 100644
--- a/riscv/processor.cc
+++ b/riscv/processor.cc
@@ -374,7 +374,7 @@ void processor_t::set_csr(int which, reg_t val)
       return set_csr(CSR_MSTATUS, (state.mstatus & ~mask) | (val & mask));
     }
     case CSR_SIP: {
-      reg_t mask = MIP_SSIP;
+      reg_t mask = MIP_SSIP & state.mideleg;
       return set_csr(CSR_MIP, (state.mip & ~mask) | (val & mask));
     }
     case CSR_SIE:
-- 
2.30.2