From e9ed4761b53160e4f55319bfe7010b380e202e6b Mon Sep 17 00:00:00 2001 From: Florent Kermarrec Date: Sun, 29 Sep 2019 16:10:44 +0200 Subject: [PATCH] soc/cores/gpio: uniformize with others cores --- litex/soc/cores/gpio.py | 3 +++ 1 file changed, 3 insertions(+) diff --git a/litex/soc/cores/gpio.py b/litex/soc/cores/gpio.py index b4ec50a3..21028898 100644 --- a/litex/soc/cores/gpio.py +++ b/litex/soc/cores/gpio.py @@ -6,18 +6,21 @@ from migen.genlib.cdc import MultiReg from litex.soc.interconnect.csr import * +# GPIO Input ---------------------------------------------------------------------------------------- class GPIOIn(Module, AutoCSR): def __init__(self, signal): self._in = CSRStatus(len(signal)) self.specials += MultiReg(signal, self._in.status) +# GPIO Output -------------------------------------------------------------------------------------- class GPIOOut(Module, AutoCSR): def __init__(self, signal): self._out = CSRStorage(len(signal)) self.comb += signal.eq(self._out.storage) +# GPIO Input/Output -------------------------------------------------------------------------------- class GPIOInOut(Module): def __init__(self, in_signal, out_signal): -- 2.30.2