From e9fe57c75e225f80156ceabbc10741c3cfee1c87 Mon Sep 17 00:00:00 2001 From: Clifford Wolf Date: Wed, 10 Aug 2016 19:32:11 +0200 Subject: [PATCH] Only allow posedge/negedge with 1 bit wide signals --- frontends/ast/genrtlil.cc | 2 ++ 1 file changed, 2 insertions(+) diff --git a/frontends/ast/genrtlil.cc b/frontends/ast/genrtlil.cc index 04cdb9416..bee2256e3 100644 --- a/frontends/ast/genrtlil.cc +++ b/frontends/ast/genrtlil.cc @@ -241,6 +241,8 @@ struct AST_INTERNAL::ProcessGenerator RTLIL::SyncRule *syncrule = new RTLIL::SyncRule; syncrule->type = child->type == AST_POSEDGE ? RTLIL::STp : RTLIL::STn; syncrule->signal = child->children[0]->genRTLIL(); + if (GetSize(syncrule->signal) != 1) + log_error("Found posedge/negedge event on a signal that is not 1 bit wide at %s:%d!\n", always->filename.c_str(), always->linenum); addChunkActions(syncrule->actions, subst_lvalue_from, subst_lvalue_to, true); proc->syncs.push_back(syncrule); } -- 2.30.2