From ea080c507a3f66ec6b5d3659ae33fa7d0a1038f3 Mon Sep 17 00:00:00 2001 From: Luke Kenneth Casson Leighton Date: Wed, 27 May 2020 16:55:10 +0100 Subject: [PATCH] comments --- src/soc/fu/alu/main_stage.py | 6 ++++-- 1 file changed, 4 insertions(+), 2 deletions(-) diff --git a/src/soc/fu/alu/main_stage.py b/src/soc/fu/alu/main_stage.py index b39d0199..28c6b4d3 100644 --- a/src/soc/fu/alu/main_stage.py +++ b/src/soc/fu/alu/main_stage.py @@ -16,14 +16,16 @@ class ALUMainStage(PipeModBase): super().__init__(pspec, "main") def ispec(self): - return ALUInputData(self.pspec) + return ALUInputData(self.pspec) # defines pipeline stage input format def ospec(self): - return ALUOutputData(self.pspec) # TODO: ALUIntermediateData + return ALUOutputData(self.pspec) # defines pipeline stage output format def elaborate(self, platform): m = Module() comb = m.d.comb + + # convenience variables cry_o, o, cr0 = self.o.xer_ca, self.o.o, self.o.cr0 ov_o = self.o.xer_ov a, b, cry_i, op = self.i.a, self.i.b, self.i.xer_ca, self.i.ctx.op -- 2.30.2