From ea0ac53f059c418d5797c495b87020f2ca2ec842 Mon Sep 17 00:00:00 2001 From: Francisco Jerez Date: Mon, 29 Jun 2015 16:50:49 +0300 Subject: [PATCH] i965/fs: Drop unused untyped surface read and atomic emit methods. Reviewed-by: Jason Ekstrand --- src/mesa/drivers/dri/i965/brw_fs.h | 7 -- src/mesa/drivers/dri/i965/brw_fs_nir.cpp | 13 +-- src/mesa/drivers/dri/i965/brw_fs_visitor.cpp | 112 ------------------- 3 files changed, 5 insertions(+), 127 deletions(-) diff --git a/src/mesa/drivers/dri/i965/brw_fs.h b/src/mesa/drivers/dri/i965/brw_fs.h index 822cd2736c4..4749c47f224 100644 --- a/src/mesa/drivers/dri/i965/brw_fs.h +++ b/src/mesa/drivers/dri/i965/brw_fs.h @@ -286,13 +286,6 @@ public: int shader_time_subindex, fs_reg value); - void emit_untyped_atomic(unsigned atomic_op, unsigned surf_index, - fs_reg dst, fs_reg offset, fs_reg src0, - fs_reg src1); - - void emit_untyped_surface_read(unsigned surf_index, fs_reg dst, - fs_reg offset); - fs_reg get_timestamp(const brw::fs_builder &bld); struct brw_reg interp_reg(int location, int channel); diff --git a/src/mesa/drivers/dri/i965/brw_fs_nir.cpp b/src/mesa/drivers/dri/i965/brw_fs_nir.cpp index d4812c55556..3e8860bafc6 100644 --- a/src/mesa/drivers/dri/i965/brw_fs_nir.cpp +++ b/src/mesa/drivers/dri/i965/brw_fs_nir.cpp @@ -1269,20 +1269,17 @@ fs_visitor::nir_emit_intrinsic(const fs_builder &bld, nir_intrinsic_instr *instr /* Emit a surface read or atomic op. */ switch (instr->intrinsic) { case nir_intrinsic_atomic_counter_read: - tmp = surface_access::emit_untyped_read( - bld, fs_reg(surface), offset, 1, 1); + tmp = emit_untyped_read(bld, fs_reg(surface), offset, 1, 1); break; case nir_intrinsic_atomic_counter_inc: - tmp = surface_access::emit_untyped_atomic( - bld, fs_reg(surface), offset, fs_reg(), - fs_reg(), 1, 1, BRW_AOP_INC); + tmp = emit_untyped_atomic(bld, fs_reg(surface), offset, fs_reg(), + fs_reg(), 1, 1, BRW_AOP_INC); break; case nir_intrinsic_atomic_counter_dec: - tmp = surface_access::emit_untyped_atomic( - bld, fs_reg(surface), offset, fs_reg(), - fs_reg(), 1, 1, BRW_AOP_PREDEC); + tmp = emit_untyped_atomic(bld, fs_reg(surface), offset, fs_reg(), + fs_reg(), 1, 1, BRW_AOP_PREDEC); break; default: diff --git a/src/mesa/drivers/dri/i965/brw_fs_visitor.cpp b/src/mesa/drivers/dri/i965/brw_fs_visitor.cpp index 5f0549c3bc0..111db8c4323 100644 --- a/src/mesa/drivers/dri/i965/brw_fs_visitor.cpp +++ b/src/mesa/drivers/dri/i965/brw_fs_visitor.cpp @@ -530,118 +530,6 @@ fs_visitor::try_replace_with_sel() return false; } -void -fs_visitor::emit_untyped_atomic(unsigned atomic_op, unsigned surf_index, - fs_reg dst, fs_reg offset, fs_reg src0, - fs_reg src1) -{ - int reg_width = dispatch_width / 8; - int length = 0; - - fs_reg *sources = ralloc_array(mem_ctx, fs_reg, 4); - - sources[0] = fs_reg(GRF, alloc.allocate(1), BRW_REGISTER_TYPE_UD); - /* Initialize the sample mask in the message header. */ - bld.exec_all().MOV(sources[0], fs_reg(0u)); - - if (stage == MESA_SHADER_FRAGMENT) { - if (((brw_wm_prog_data*)this->prog_data)->uses_kill) { - bld.exec_all() - .MOV(component(sources[0], 7), brw_flag_reg(0, 1)); - } else { - bld.exec_all() - .MOV(component(sources[0], 7), - retype(brw_vec1_grf(1, 7), BRW_REGISTER_TYPE_UD)); - } - } else { - /* The execution mask is part of the side-band information sent together with - * the message payload to the data port. It's implicitly ANDed with the sample - * mask sent in the header to compute the actual set of channels that execute - * the atomic operation. - */ - assert(stage == MESA_SHADER_VERTEX || stage == MESA_SHADER_COMPUTE); - bld.exec_all() - .MOV(component(sources[0], 7), fs_reg(0xffffu)); - } - length++; - - /* Set the atomic operation offset. */ - sources[1] = vgrf(glsl_type::uint_type); - bld.MOV(sources[1], offset); - length++; - - /* Set the atomic operation arguments. */ - if (src0.file != BAD_FILE) { - sources[length] = vgrf(glsl_type::uint_type); - bld.MOV(sources[length], src0); - length++; - } - - if (src1.file != BAD_FILE) { - sources[length] = vgrf(glsl_type::uint_type); - bld.MOV(sources[length], src1); - length++; - } - - int mlen = 1 + (length - 1) * reg_width; - fs_reg src_payload = fs_reg(GRF, alloc.allocate(mlen), - BRW_REGISTER_TYPE_UD); - bld.LOAD_PAYLOAD(src_payload, sources, length, 1); - - /* Emit the instruction. */ - fs_inst *inst = bld.emit(SHADER_OPCODE_UNTYPED_ATOMIC, dst, src_payload, - fs_reg(surf_index), fs_reg(atomic_op)); - inst->mlen = mlen; -} - -void -fs_visitor::emit_untyped_surface_read(unsigned surf_index, fs_reg dst, - fs_reg offset) -{ - int reg_width = dispatch_width / 8; - - fs_reg *sources = ralloc_array(mem_ctx, fs_reg, 2); - - sources[0] = fs_reg(GRF, alloc.allocate(1), BRW_REGISTER_TYPE_UD); - /* Initialize the sample mask in the message header. */ - bld.exec_all() - .MOV(sources[0], fs_reg(0u)); - - if (stage == MESA_SHADER_FRAGMENT) { - if (((brw_wm_prog_data*)this->prog_data)->uses_kill) { - bld.exec_all() - .MOV(component(sources[0], 7), brw_flag_reg(0, 1)); - } else { - bld.exec_all() - .MOV(component(sources[0], 7), - retype(brw_vec1_grf(1, 7), BRW_REGISTER_TYPE_UD)); - } - } else { - /* The execution mask is part of the side-band information sent together with - * the message payload to the data port. It's implicitly ANDed with the sample - * mask sent in the header to compute the actual set of channels that execute - * the atomic operation. - */ - assert(stage == MESA_SHADER_VERTEX || stage == MESA_SHADER_COMPUTE); - bld.exec_all() - .MOV(component(sources[0], 7), fs_reg(0xffffu)); - } - - /* Set the surface read offset. */ - sources[1] = vgrf(glsl_type::uint_type); - bld.MOV(sources[1], offset); - - int mlen = 1 + reg_width; - fs_reg src_payload = fs_reg(GRF, alloc.allocate(mlen), - BRW_REGISTER_TYPE_UD); - fs_inst *inst = bld.LOAD_PAYLOAD(src_payload, sources, 2, 1); - - /* Emit the instruction. */ - inst = bld.emit(SHADER_OPCODE_UNTYPED_SURFACE_READ, dst, src_payload, - fs_reg(surf_index), fs_reg(1)); - inst->mlen = mlen; -} - /** Emits a dummy fragment shader consisting of magenta for bringup purposes. */ void fs_visitor::emit_dummy_fs() -- 2.30.2