From ea0b6258ab392b6186ee5d75a75da944b25d0392 Mon Sep 17 00:00:00 2001 From: Miodrag Milanovic Date: Wed, 26 Jun 2019 18:34:34 +0200 Subject: [PATCH] Simulation model verilog fix --- techlibs/ecp5/cells_sim.v | 13 ------------- techlibs/xilinx/cells_sim.v | 2 +- 2 files changed, 1 insertion(+), 14 deletions(-) diff --git a/techlibs/ecp5/cells_sim.v b/techlibs/ecp5/cells_sim.v index 2458c1ca0..07fadfa10 100644 --- a/techlibs/ecp5/cells_sim.v +++ b/techlibs/ecp5/cells_sim.v @@ -281,19 +281,6 @@ endmodule // --------------------------------------- -module OB(input I, output O); -assign O = I; -endmodule - -// --------------------------------------- - -module BB(input I, T, output O, inout B); -assign B = T ? 1'bz : I; -assign O = B; -endmodule - -// --------------------------------------- - module INV(input A, output Z); assign Z = !A; endmodule diff --git a/techlibs/xilinx/cells_sim.v b/techlibs/xilinx/cells_sim.v index 50d588a9e..f4598dcf4 100644 --- a/techlibs/xilinx/cells_sim.v +++ b/techlibs/xilinx/cells_sim.v @@ -282,7 +282,7 @@ module RAM32X1D ( output DPO, SPO, input D, WCLK, WE, input A0, A1, A2, A3, A4, - input DPRA0, DPRA1, DPRA2, DPRA3, DPRA4, + input DPRA0, DPRA1, DPRA2, DPRA3, DPRA4 ); parameter INIT = 32'h0; parameter IS_WCLK_INVERTED = 1'b0; -- 2.30.2