From ea1b5cc179f519d73be3a745de519571c887c967 Mon Sep 17 00:00:00 2001 From: Paul Mackerras Date: Wed, 3 Jun 2020 10:40:52 +1000 Subject: [PATCH] Re: [libre-riscv-dev] [OpenPOWER-HDL-Cores] microwatt decoder tables: M-Form and X-Form switched RS and RB --- 11/563a806447321260847212ef84b3a76d52eba6 | 139 ++++++++++++++++++++++ 1 file changed, 139 insertions(+) create mode 100644 11/563a806447321260847212ef84b3a76d52eba6 diff --git a/11/563a806447321260847212ef84b3a76d52eba6 b/11/563a806447321260847212ef84b3a76d52eba6 new file mode 100644 index 0000000..bcd8248 --- /dev/null +++ b/11/563a806447321260847212ef84b3a76d52eba6 @@ -0,0 +1,139 @@ +Return-path: +Envelope-to: publicinbox@libre-riscv.org +Delivery-date: Wed, 03 Jun 2020 01:41:29 +0100 +Received: from localhost ([::1] helo=libre-riscv.org) + by libre-soc.org with esmtp (Exim 4.89) + (envelope-from ) + id 1jgHTE-0008Tm-Pd; Wed, 03 Jun 2020 01:41:28 +0100 +Received: from ozlabs.org ([203.11.71.1]) + by libre-soc.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) + (Exim 4.89) (envelope-from ) id 1jgHTC-0008Tg-5W + for libre-riscv-dev@lists.libre-riscv.org; Wed, 03 Jun 2020 01:41:26 +0100 +Received: by ozlabs.org (Postfix, from userid 1003) + id 49c9835BP6z9sT6; Wed, 3 Jun 2020 10:41:23 +1000 (AEST) +DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=ozlabs.org; s=201707; + t=1591144883; bh=a8TKQ2hUnsee5YsTUiGVL4doUwqwDujleYeZiEi+YEY=; + h=Date:From:To:Cc:Subject:References:In-Reply-To:From; + b=Dhde+BlurCDJjNcciVmq67FRSOhRNN5JxdZOcP52UMs92F1qSTlUVZrHiG5ixUpiF + PPPeQA/0E0hJpMsWPCu6vtqZALx5WzSeyMorUWCVKHCDXLIAWV70RQ07HMuf5v386h + PKlg/uiVGTWS/oEZK28d+k2+480xTxpX6UBkVSWuO5a+PRudWylHbO0WPKTvCUZSeC + alxdIDf7PJVm/GOBoZuAo2UUdLdSTdvOukxqRC5MUsH+Ubfa9OW7c8j+9ebiaZg6n2 + 4Yd/zVXehQ1PVkyvXem9IBSjx/MH7CcnUnrcMAWLHm7Jcbr18c8y/FHscBGJ9K0dho + mpTbTYtKHeDYg== +Date: Wed, 3 Jun 2020 10:40:52 +1000 +From: Paul Mackerras +To: Luke Kenneth Casson Leighton +Message-ID: <20200603004052.GA725968@thinks.paulus.ozlabs.org> +References: + <20200601231311.GA428673@thinks.paulus.ozlabs.org> + + +MIME-Version: 1.0 +Content-Disposition: inline +In-Reply-To: +Subject: Re: [libre-riscv-dev] [OpenPOWER-HDL-Cores] microwatt decoder + tables: M-Form and X-Form switched RS and RB +X-BeenThere: libre-riscv-dev@lists.libre-riscv.org +X-Mailman-Version: 2.1.23 +Precedence: list +List-Id: Libre-RISCV General Development + +List-Unsubscribe: , + +List-Archive: +List-Post: +List-Help: +List-Subscribe: , + +Reply-To: Libre-RISCV General Development + +Cc: "openpower-hdl-cores@mailinglist.openpowerfoundation.org" + , + Libre-RISCV General Development +Content-Type: text/plain; charset="utf-8" +Content-Transfer-Encoding: base64 +Errors-To: libre-riscv-dev-bounces@lists.libre-riscv.org +Sender: "libre-riscv-dev" + +T24gVHVlLCBKdW4gMDIsIDIwMjAgYXQgMDE6MTA6MzdQTSArMDEwMCwgTHVrZSBLZW5uZXRoIENh +c3NvbiBMZWlnaHRvbiB3cm90ZToKPiBvay4gIGludGVyZXN0aW5nLiAgaSBzdGFydCB0byBzZWUg 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