From ea2b06b285884242abd07ce18bd36d0c71baf63e Mon Sep 17 00:00:00 2001 From: Florent Kermarrec Date: Fri, 19 Dec 2014 20:16:37 +0100 Subject: [PATCH] fix phy datapath, first communications between SATACON and a HDD... :) --- lib/sata/phy/datapath.py | 22 ++++++++++++++-------- targets/test.py | 5 +++++ test/test_identify.py | 2 ++ 3 files changed, 21 insertions(+), 8 deletions(-) diff --git a/lib/sata/phy/datapath.py b/lib/sata/phy/datapath.py index 66623504..8930955f 100644 --- a/lib/sata/phy/datapath.py +++ b/lib/sata/phy/datapath.py @@ -12,25 +12,30 @@ class SATAPHYDatapathRX(Module): ### # width convertion (16 to 32) and byte alignment + byte_alignment = Signal() last_charisk = Signal(2) last_data = Signal(16) - self.sync += \ + self.sync.sata_rx += \ If(self.sink.stb & self.sink.ack, If(self.sink.charisk != 0, - last_charisk.eq(self.sink.charisk) + byte_alignment.eq(self.sink.charisk[1]) ), + last_charisk.eq(self.sink.charisk), last_data.eq(self.sink.data) ) - self.converter = Converter(phy_description(16), phy_description(32), reverse=True) + converter = Converter(phy_description(16), phy_description(32), reverse=False) + self.converter = InsertReset(RenameClockDomains(converter, "sata_rx")) self.comb += [ self.converter.sink.stb.eq(self.sink.stb), - self.converter.sink.charisk.eq(0b01), - If(last_charisk[1], - self.converter.sink.data.eq(Cat(self.sink.data[8:], last_data[:8])) + If(byte_alignment, + self.converter.sink.charisk.eq(Cat(last_charisk[1], self.sink.charisk[0])), + self.converter.sink.data.eq(Cat(last_data[8:], self.sink.data[:8])) ).Else( + self.converter.sink.charisk.eq(self.sink.charisk), self.converter.sink.data.eq(self.sink.data) ), - self.sink.ack.eq(self.converter.sink.ack) + self.sink.ack.eq(self.converter.sink.ack), + self.converter.reset.eq(self.converter.source.charisk[2:] != 0) ] # clock domain crossing @@ -65,7 +70,8 @@ class SATAPHYDatapathTX(Module): self.comb += Record.connect(self.sink, fifo.sink) # width convertion (32 to 16) - self.converter = Converter(phy_description(32), phy_description(16), reverse=True) + converter = Converter(phy_description(32), phy_description(16), reverse=False) + self.converter = RenameClockDomains(converter, "sata_tx") self.comb += [ Record.connect(self.fifo.source, self.converter.sink), Record.connect(self.converter.source, self.source) diff --git a/targets/test.py b/targets/test.py index 8115d66a..bc2786f2 100644 --- a/targets/test.py +++ b/targets/test.py @@ -207,6 +207,11 @@ class TestDesign(UART2WB, AutoCSR): self.sata_phy.sink.data, self.sata_phy.sink.charisk, + self.sata_phy.datapath.tx.sink.stb, + self.sata_phy.datapath.tx.sink.data, + self.sata_phy.datapath.tx.sink.charisk, + self.sata_phy.datapath.tx.sink.ack, + self.sata_con.sink.stb, self.sata_con.sink.sop, self.sata_con.sink.eop, diff --git a/test/test_identify.py b/test/test_identify.py index 513bded4..5585b822 100644 --- a/test/test_identify.py +++ b/test/test_identify.py @@ -1,8 +1,10 @@ +import time from config import * from miscope.host.drivers import MiLaDriver mila = MiLaDriver(wb.regs, "mila", use_rle=False) wb.open() +regs = wb.regs ### trigger0 = mila.sata_con_sink_stb_o*1 mask0 = mila.sata_con_sink_stb_m -- 2.30.2