From ea306d058e0bc62ce8debd22b83a74df45178f6e Mon Sep 17 00:00:00 2001
From: lkcl <lkcl@web>
Date: Sun, 3 May 2020 14:20:43 +0100
Subject: [PATCH]

---
 3d_gpu/architecture/regfile.mdwn | 14 ++++++++++++++
 1 file changed, 14 insertions(+)
 create mode 100644 3d_gpu/architecture/regfile.mdwn

diff --git a/3d_gpu/architecture/regfile.mdwn b/3d_gpu/architecture/regfile.mdwn
new file mode 100644
index 000000000..cd735fc3b
--- /dev/null
+++ b/3d_gpu/architecture/regfile.mdwn
@@ -0,0 +1,14 @@
+# Register Files
+
+A minimum of 3 register files are required for POWER:
+
+* Floating-point
+* Integer
+* Control and Condition Code Registers (CR0-7, CTR, LR)
+* SPRs (Special Purpose Registers)
+
+The FP and Integer registers need to be a massive 128 x 64-bit.
+
+# Connectivity between regfiles and Function Units
+
+[[!img regfile_hilo_32_odd_even.reg]]
-- 
2.30.2