From ea41df6fdf78eb36ced514f77af36a0a04589401 Mon Sep 17 00:00:00 2001 From: Cesar Strauss Date: Sat, 3 Apr 2021 15:40:31 -0300 Subject: [PATCH] Allow the Simulator to handle back-to-back signaling from TestIssuer TestIssuer can signal the end of an instruction and, after skipping mask bits, signal the end of the VL loop, right on the following cycle. Since there is no handshake between TestIssuer and Simulator, we need to remove any wait state that would cause the Simulator to miss the one-clock pulse. --- src/soc/simple/test/test_runner.py | 7 ------- 1 file changed, 7 deletions(-) diff --git a/src/soc/simple/test/test_runner.py b/src/soc/simple/test/test_runner.py index b6be2f3a..2cfd60ee 100644 --- a/src/soc/simple/test/test_runner.py +++ b/src/soc/simple/test/test_runner.py @@ -259,12 +259,8 @@ class TestRunner(FHDLTestCase): counter = counter + 1 # wait until executed - # wait for insn_done high while not (yield issuer.insn_done): yield - # wait for insn_done low - while (yield issuer.insn_done): - yield # set up simulated instruction (in simdec2) try: @@ -289,9 +285,6 @@ class TestRunner(FHDLTestCase): yield yield - # wait one cycle for registers to settle - yield - # register check yield from check_regs(self, sim, core, test, code) -- 2.30.2