From ea48f44b90214012b8d92f4f7ab9627665e9300b Mon Sep 17 00:00:00 2001
From: Florent Kermarrec <florent@enjoy-digital.fr>
Date: Fri, 23 Jan 2015 00:31:57 +0100
Subject: [PATCH] add LiteScopeLA example

---
 litescope/host/driver.py |  2 +-
 targets/simple.py        | 27 +++++++++++++++++++++------
 test/Makefile            |  3 +++
 test/test_la.py          | 20 ++++++++++++++++++++
 4 files changed, 45 insertions(+), 7 deletions(-)
 create mode 100644 test/test_la.py

diff --git a/litescope/host/driver.py b/litescope/host/driver.py
index 0d6beb64..289a407e 100644
--- a/litescope/host/driver.py
+++ b/litescope/host/driver.py
@@ -139,7 +139,7 @@ class LiteScopeLADriver():
 	def build(self):
 		for key, value in self.regs.d.items():
 			if self.name == key[:len(self.name)]:
-				key = key.replace(self.name + "_")
+				key = key.replace(self.name + "_", "")
 				setattr(self, key, value)
 		value = 1
 		for name, length in self.layout:
diff --git a/targets/simple.py b/targets/simple.py
index 13f734af..240264f3 100644
--- a/targets/simple.py
+++ b/targets/simple.py
@@ -3,8 +3,6 @@ import os
 from migen.bank import csrgen
 from migen.bus import wishbone, csr
 from migen.bus import wishbone2csr
-from migen.genlib.cdc import *
-from migen.genlib.resetsync import AsyncResetSynchronizer
 from migen.bank.description import *
 
 from misoclib import identifier
@@ -12,7 +10,8 @@ from misoclib import identifier
 from litescope.common import *
 from litescope.bridge.uart2wb import LiteScopeUART2WB
 from litescope.frontend.io import LiteScopeIO
-
+from litescope.frontend.la import LiteScopeLA
+from litescope.core.trigger import LiteScopeTerm
 
 class _CRG(Module):
 	def __init__(self, clk_in):
@@ -75,11 +74,11 @@ class GenSoC(Module):
 class LiteScopeSoC(GenSoC, AutoCSR):
 	default_platform = "de0nano"
 	csr_map = {
-		"io":	10
+		"io":	10,
+		"la":	11
 	}
 	csr_map.update(GenSoC.csr_map)
-
-	def __init__(self, platform, export_mila=False):
+	def __init__(self, platform, export_conf=False):
 		clk_freq = 50*1000000
 		GenSoC.__init__(self, platform, clk_freq)
 		self.submodules.crg = _CRG(platform.request("clk50"))
@@ -88,4 +87,20 @@ class LiteScopeSoC(GenSoC, AutoCSR):
 		self.leds = Cat(*[platform.request("user_led", i) for i in range(8)])
 		self.comb += self.leds.eq(self.io.o)
 
+		cnt0 = Signal(8)
+		cnt1 = Signal(8)
+		self.sync += [
+			cnt0.eq(cnt0+1),
+			cnt1.eq(cnt1+2)
+		]
+		debug = (
+			cnt0,
+			cnt1
+		)
+		self.submodules.la = LiteScopeLA(depth=512, dat=Cat(*debug))
+		self.la.add_port(LiteScopeTerm)
+		if export_conf:
+			self.la.export(self, debug, "./test/la.csv")
+
+
 default_subtarget = LiteScopeSoC
diff --git a/test/Makefile b/test/Makefile
index cba12bec..da182725 100644
--- a/test/Makefile
+++ b/test/Makefile
@@ -8,3 +8,6 @@ test_regs:
 
 test_io:
 	$(CMD) test_io.py
+
+test_la:
+	$(CMD) test_la.py
diff --git a/test/test_la.py b/test/test_la.py
new file mode 100644
index 00000000..6e1fb943
--- /dev/null
+++ b/test/test_la.py
@@ -0,0 +1,20 @@
+from config import *
+from litescope.host.driver import LiteScopeLADriver
+
+wb.open()
+###
+la = LiteScopeLADriver(wb.regs, "la")
+
+cond = {"cnt0"	:	128} # trigger on cnt0 = 128
+la.prog_term(port=0, cond=cond)
+la.prog_sum("term")
+la.trigger(offset=128, length=256)
+
+la.wait_done()
+la.read()
+
+la.export("dump.vcd")
+la.export("dump.csv")
+la.export("dump.py")
+###
+wb.close()
-- 
2.30.2