From ea52df816d423cd956a392ab1eb99df187cded65 Mon Sep 17 00:00:00 2001 From: Tony Gutierrez Date: Thu, 5 Jul 2018 19:37:04 -0400 Subject: [PATCH] arch-gcn3: Add support for rd/wr EXEC_HI to operand class Change-Id: Ib22dd604f88ea56801964235082835002deffca1 Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/29944 Maintainer: Anthony Gutierrez Tested-by: kokoro Reviewed-by: Matt Sinclair --- src/arch/gcn3/operand.hh | 36 +++++++++++++++++++++++++++++++++++- 1 file changed, 35 insertions(+), 1 deletion(-) diff --git a/src/arch/gcn3/operand.hh b/src/arch/gcn3/operand.hh index 7f70fab74..960d05eee 100644 --- a/src/arch/gcn3/operand.hh +++ b/src/arch/gcn3/operand.hh @@ -435,13 +435,30 @@ namespace Gcn3ISA if (!isScalarReg(_opIdx)) { if (_opIdx == REG_EXEC_LO) { - uint64_t new_exec_mask_val(0); + ScalarRegU64 new_exec_mask_val(0); std::memcpy((void*)&new_exec_mask_val, (void*)srfData.data(), sizeof(new_exec_mask_val)); VectorMask new_exec_mask(new_exec_mask_val); wf->execMask() = new_exec_mask; DPRINTF(GPUSRF, "Write EXEC\n"); DPRINTF(GPUSRF, "EXEC = %#x\n", new_exec_mask_val); + } else if (_opIdx == REG_EXEC_HI) { + /** + * If we're writing only the upper half of the EXEC mask + * this ought to be a single dword operand. + */ + assert(NumDwords == 1); + ScalarRegU32 new_exec_mask_hi_val(0); + ScalarRegU64 new_exec_mask_val + = wf->execMask().to_ullong(); + std::memcpy((void*)&new_exec_mask_hi_val, + (void*)srfData.data(), sizeof(new_exec_mask_hi_val)); + replaceBits(new_exec_mask_val, 63, 32, + new_exec_mask_hi_val); + VectorMask new_exec_mask(new_exec_mask_val); + wf->execMask() = new_exec_mask; + DPRINTF(GPUSRF, "Write EXEC\n"); + DPRINTF(GPUSRF, "EXEC = %#x\n", new_exec_mask_val); } else { _gpuDynInst->writeMiscReg(_opIdx, srfData[0]); } @@ -505,6 +522,23 @@ namespace Gcn3ISA DPRINTF(GPUSRF, "EXEC = %#x\n", exec_mask); } break; + case REG_EXEC_HI: + { + /** + * If we're reading only the upper half of the EXEC mask + * this ought to be a single dword operand. + */ + assert(NumDwords == 1); + ScalarRegU64 exec_mask = _gpuDynInst->wavefront() + ->execMask().to_ullong(); + + ScalarRegU32 exec_mask_hi = bits(exec_mask, 63, 32); + std::memcpy((void*)srfData.data(), (void*)&exec_mask_hi, + sizeof(srfData)); + DPRINTF(GPUSRF, "Read EXEC_HI\n"); + DPRINTF(GPUSRF, "EXEC_HI = %#x\n", exec_mask_hi); + } + break; case REG_SRC_SWDA: case REG_SRC_DPP: case REG_SRC_LITERAL: -- 2.30.2