From ea54b5ea61ee242e1dfa7f257a10095f267b8171 Mon Sep 17 00:00:00 2001 From: Eddie Hung Date: Tue, 8 Oct 2019 12:41:24 -0700 Subject: [PATCH] Revert "Be mindful that sigmap(wire) could have dupes when checking \init" This reverts commit f46ac1df9f8847dac9d9851f2f948d93a1064ff1. --- passes/sat/sat.cc | 5 +---- 1 file changed, 1 insertion(+), 4 deletions(-) diff --git a/passes/sat/sat.cc b/passes/sat/sat.cc index 93a4f225e..430bba1e8 100644 --- a/passes/sat/sat.cc +++ b/passes/sat/sat.cc @@ -265,18 +265,15 @@ struct SatHelper RTLIL::SigSpec rhs = it.second->attributes.at("\\init"); log_assert(lhs.size() == rhs.size()); - dict seen_init; RTLIL::SigSpec removed_bits; for (int i = 0; i < lhs.size(); i++) { RTLIL::SigSpec bit = lhs.extract(i, 1); - if (rhs[i] == State::Sx || !satgen.initial_state.check_all(bit) || seen_init.at(bit, rhs[i]) != rhs[i]) { + if (rhs[i] == State::Sx || !satgen.initial_state.check_all(bit)) { removed_bits.append(bit); lhs.remove(i, 1); rhs.remove(i, 1); i--; } - else - seen_init[bit] = rhs[i]; } if (removed_bits.size()) -- 2.30.2