From ea5e4e1b41114abcc8f810af71ae07491a242785 Mon Sep 17 00:00:00 2001 From: Luke Kenneth Casson Leighton Date: Tue, 21 Dec 2021 16:04:56 +0000 Subject: [PATCH] only add pc_i in DMI mode running MMU test --- libresoc/core.py | 4 ++-- sim.py | 4 +++- 2 files changed, 5 insertions(+), 3 deletions(-) diff --git a/libresoc/core.py b/libresoc/core.py index f22925b..ec1c029 100644 --- a/libresoc/core.py +++ b/libresoc/core.py @@ -241,8 +241,6 @@ class LibreSoC(CPU): i_rst = ResetSignal() | self.reset, # Monitoring / Debugging - i_pc_i = Signal(64), - i_pc_i_ok = 0, i_core_bigendian_i = 0, # Signal(), o_busy_o = Signal(), # not connected o_memerr_o = Signal(), # not connected @@ -271,6 +269,8 @@ class LibreSoC(CPU): i_dmi_we_i = self.dmi_wr, o_dmi_ack_o = self.dmi_ack, )) + self.cpu_params['i_pc_i'] = Signal(64) + self.cpu_params['i_pc_i_ok'] = 0 # add clock select, pll output if "ls180" in variant and "pll" not in variant: diff --git a/sim.py b/sim.py index 550339e..accac4f 100755 --- a/sim.py +++ b/sim.py @@ -64,7 +64,9 @@ class LibreSoCSim(SoCSDRAM): # "tests/decrementer/decrementer.bin" #ram_fname = "/home/lkcl/src/libresoc/microwatt/" \ # "hello_world/hello_world.bin" - ram_fname = None + ram_fname = "/home/lkcl/src/libresoc/microwatt/" \ + "tests/mmu/mmu.bin" + #ram_fname = None # reserve XICS ICP and XICS memory addresses. self.mem_map['xicsicp'] = 0xc0004000 -- 2.30.2