From ea5eb08d03b3baae0bb1acbe47dc67f5be7dbd64 Mon Sep 17 00:00:00 2001 From: Luke Kenneth Casson Leighton Date: Sat, 16 May 2020 02:10:30 +0100 Subject: [PATCH] add comment in branch test_pipe_caller.py about decoding needed of op to set spr1/2/3 correctly --- src/soc/branch/test/test_pipe_caller.py | 9 +++++++-- 1 file changed, 7 insertions(+), 2 deletions(-) diff --git a/src/soc/branch/test/test_pipe_caller.py b/src/soc/branch/test/test_pipe_caller.py index 1553514b..335b63ed 100644 --- a/src/soc/branch/test/test_pipe_caller.py +++ b/src/soc/branch/test/test_pipe_caller.py @@ -97,7 +97,6 @@ class BranchTestCase(FHDLTestCase): self.run_tst_program(Program(lst), initial_sprs=initial_sprs, initial_cr=cr) - def test_ilang(self): rec = CompBROpSubset() @@ -159,12 +158,18 @@ class TestRunner(FHDLTestCase): yield instruction.eq(ins) # raw binary instr. yield branch.p.data_i.cia.eq(simulator.pc.CIA.value) yield branch.p.data_i.cr.eq(simulator.cr.get_range().value) + # note, here, the op will need further decoding in order + # to set the correct SPRs on SPR1/2/3. op_bc* require + # spr2 to be set to CTR, op_bctar require spr1 to be + # set to TAR, op_bclr* require spr1 to be set to LR. + # if op_sc*, op_rf* and op_hrfid are to be added here + # then additional op-decoding is required, accordingly yield branch.p.data_i.spr2.eq(simulator.spr['CTR'].value) print(f"cr0: {simulator.crl[0].get_range()}") yield Settle() fn_unit = yield pdecode2.e.fn_unit self.assertEqual(fn_unit, Function.BRANCH.value, code) - yield + yield yield opname = code.split(' ')[0] prev_nia = simulator.pc.NIA.value -- 2.30.2