From ea62be9c42d1e48951a07c34ab0104242f49b530 Mon Sep 17 00:00:00 2001
From: lkcl <lkcl@web>
Date: Tue, 28 Nov 2023 20:03:03 +0000
Subject: [PATCH]

---
 meetings/sync_up/sync_up_2023-11-28.mdwn | 7 +++++--
 1 file changed, 5 insertions(+), 2 deletions(-)

diff --git a/meetings/sync_up/sync_up_2023-11-28.mdwn b/meetings/sync_up/sync_up_2023-11-28.mdwn
index 19eb54d79..52bd53fb3 100644
--- a/meetings/sync_up/sync_up_2023-11-28.mdwn
+++ b/meetings/sync_up/sync_up_2023-11-28.mdwn
@@ -23,9 +23,12 @@
 * Clarification of the scope of new grants.
   See [[meetings/dmitry_2023-11-24]] notes for more context.
 
-- SimpleV prefix proposal from 2019: <https://libre-soc.org/simple_v_extension/sv_prefix_proposal/>
+Meeting notes:
+
+- Deprecated SimpleV prefix format from 2019: <https://libre-soc.org/simple_v_extension/sv_prefix_proposal/>
 - RISC-V example extension: <https://github.com/riscv-software-src/riscv-isa-sim/blob/master/customext/cflush.cc>
-- The first step is to make modifications to `svanalysis.py` to classify the RISC-V instructions.
+- The first step is to make modifications to `sv_analysis.py` to classify the RISC-V instructions.
+  <https://git.libre-soc.org/?p=openpower-isa.git;a=blob;f=src/openpower/sv/sv_analysis.py;hb=HEAD>
 - Standard RISC-V opcode format: <https://github.com/riscv/riscv-opcodes>
 
 - [bug #980](https://bugs.libre-soc.org/show_bug.cgi?id=980)
-- 
2.30.2