From ea6708046219aa358532c8a771f15a35f3114eb0 Mon Sep 17 00:00:00 2001 From: Florent Kermarrec Date: Mon, 13 Apr 2015 15:44:04 +0200 Subject: [PATCH] litesata: pep8 (E225) --- misoclib/mem/litesata/core/link/cont.py | 2 +- misoclib/mem/litesata/example_designs/test/bist.py | 10 +++++----- .../mem/litesata/example_designs/test/tools.py | 4 ++-- misoclib/mem/litesata/test/command_tb.py | 2 +- misoclib/mem/litesata/test/common.py | 2 +- misoclib/mem/litesata/test/cont_tb.py | 2 +- misoclib/mem/litesata/test/crc_tb.py | 4 ++-- misoclib/mem/litesata/test/hdd.py | 14 +++++++------- misoclib/mem/litesata/test/link_tb.py | 2 +- misoclib/mem/litesata/test/phy_datapath_tb.py | 6 +++--- misoclib/mem/litesata/test/scrambler_tb.py | 4 ++-- 11 files changed, 26 insertions(+), 26 deletions(-) diff --git a/misoclib/mem/litesata/core/link/cont.py b/misoclib/mem/litesata/core/link/cont.py index ddd3ed89..6a62193f 100644 --- a/misoclib/mem/litesata/core/link/cont.py +++ b/misoclib/mem/litesata/core/link/cont.py @@ -47,7 +47,7 @@ class LiteSATACONTInserter(Module): Record.connect(sink, source), If(sink.stb, If(~change, - counter.ce.eq(sink.ack & (counter.value !=2)), + counter.ce.eq(sink.ack & (counter.value != 2)), # insert CONT If(counter.value == 1, source.charisk.eq(0b0001), diff --git a/misoclib/mem/litesata/example_designs/test/bist.py b/misoclib/mem/litesata/example_designs/test/bist.py index 57edf15a..40cf5177 100644 --- a/misoclib/mem/litesata/example_designs/test/bist.py +++ b/misoclib/mem/litesata/example_designs/test/bist.py @@ -30,7 +30,7 @@ class LiteSATABISTUnitDriver: self.frequency = regs.identifier_frequency.read() self.time = 0 for s in ["start", "sector", "count", "loops", "random", "done", "aborted", "errors", "cycles"]: - setattr(self, s, getattr(regs, name + "_"+ s)) + setattr(self, s, getattr(regs, name + "_" + s)) def run(self, sector, count, loops, random, blocking=True, hw_timer=True): self.sector.write(sector) @@ -73,7 +73,7 @@ class LiteSATABISTIdentifyDriver: self.regs = regs self.name = name for s in ["start", "done", "source_stb", "source_ack", "source_data"]: - setattr(self, s, getattr(regs, name + "_identify_"+ s)) + setattr(self, s, getattr(regs, name + "_identify_" + s)) self.data = [] def read_fifo(self): @@ -123,7 +123,7 @@ class LiteSATABISTIdentifyDriver: info = "Serial Number: " + self.serial_number + "\n" info += "Firmware Revision: " + self.firmware_revision + "\n" info += "Model Number: " + self.model_number + "\n" - info += "Capacity: %3.2f GB\n" %((self.total_sectors*logical_sector_size)/GB) + info += "Capacity: {:3.2f} GB\n".format((self.total_sectors*logical_sector_size)/GB) for k, v in self.capabilities.items(): info += k + ": " + str(v) + "\n" print(info, end="") @@ -189,9 +189,9 @@ if __name__ == "__main__": if not read_done: retry += 1 - print("sector=%d(%dMB) wr_speed=%4.2fMB/s rd_speed=%4.2fMB/s errors=%d retry=%d" %( + print("sector={:d}({:d}MB) wr_speed={:4.2f}MB/s rd_speed={:4.2f}MB/s errors={:d} retry={:d}".format( sector, - run_sectors*logical_sector_size/MB, + run_sectors*logical_sector_size/MB, write_speed/MB, read_speed/MB, write_errors + read_errors, diff --git a/misoclib/mem/litesata/example_designs/test/tools.py b/misoclib/mem/litesata/example_designs/test/tools.py index 6afd3df5..546d2bea 100644 --- a/misoclib/mem/litesata/example_designs/test/tools.py +++ b/misoclib/mem/litesata/example_designs/test/tools.py @@ -37,11 +37,11 @@ def link_trace(mila, tx_data_name, rx_data_name): rx_data = var.values for i in range(len(tx_data)): - tx = "%08x " %tx_data[i] + tx = "{:08x} ".format(tx_data[i]) tx += decode_primitive(tx_data[i]) tx += " "*(16-len(tx)) - rx = "%08x " %rx_data[i] + rx = "{:08x} ".format(rx_data[i]) rx += decode_primitive(rx_data[i]) rx += " "*(16-len(rx)) diff --git a/misoclib/mem/litesata/test/command_tb.py b/misoclib/mem/litesata/test/command_tb.py index bc474493..4dd67709 100644 --- a/misoclib/mem/litesata/test/command_tb.py +++ b/misoclib/mem/litesata/test/command_tb.py @@ -93,7 +93,7 @@ class TB(Module): # check results s, l, e = check(write_data, read_data) - print("shift "+ str(s) + " / length " + str(l) + " / errors " + str(e)) + print("shift " + str(s) + " / length " + str(l) + " / errors " + str(e)) if __name__ == "__main__": run_simulation(TB(), ncycles=2048, vcd_name="my.vcd", keep_files=True) diff --git a/misoclib/mem/litesata/test/common.py b/misoclib/mem/litesata/test/common.py index 4f669617..6472b97d 100644 --- a/misoclib/mem/litesata/test/common.py +++ b/misoclib/mem/litesata/test/common.py @@ -24,7 +24,7 @@ def check(p1, p2): else: ref, res = p2, p1 shift = 0 - while((ref[0] != res[0]) and (len(res)>1)): + while((ref[0] != res[0]) and (len(res) > 1)): res.pop(0) shift += 1 length = min(len(ref), len(res)) diff --git a/misoclib/mem/litesata/test/cont_tb.py b/misoclib/mem/litesata/test/cont_tb.py index 7010fe35..e0fd614d 100644 --- a/misoclib/mem/litesata/test/cont_tb.py +++ b/misoclib/mem/litesata/test/cont_tb.py @@ -92,7 +92,7 @@ class TB(Module): # check results s, l, e = check(streamer_packet, self.logger.packet) - print("shift "+ str(s) + " / length " + str(l) + " / errors " + str(e)) + print("shift " + str(s) + " / length " + str(l) + " / errors " + str(e)) if __name__ == "__main__": diff --git a/misoclib/mem/litesata/test/crc_tb.py b/misoclib/mem/litesata/test/crc_tb.py index 51fe7a9d..feccf565 100644 --- a/misoclib/mem/litesata/test/crc_tb.py +++ b/misoclib/mem/litesata/test/crc_tb.py @@ -15,7 +15,7 @@ class TB(Module): def get_c_crc(self, datas): stdin = "" for data in datas: - stdin += "0x%08x " %data + stdin += "0x{:08x} ".format(data) stdin += "exit" with subprocess.Popen("./crc", stdin=subprocess.PIPE, stdout=subprocess.PIPE) as process: process.stdin.write(stdin.encode("ASCII")) @@ -52,7 +52,7 @@ class TB(Module): # check results s, l, e = check(c_crc, sim_crc) - print("shift "+ str(s) + " / length " + str(l) + " / errors " + str(e)) + print("shift " + str(s) + " / length " + str(l) + " / errors " + str(e)) if __name__ == "__main__": from migen.sim.generic import run_simulation diff --git a/misoclib/mem/litesata/test/hdd.py b/misoclib/mem/litesata/test/hdd.py index 50663442..c1b9c3d4 100644 --- a/misoclib/mem/litesata/test/hdd.py +++ b/misoclib/mem/litesata/test/hdd.py @@ -75,11 +75,11 @@ class PHYLayer(Module): yield from self.rx.receive() def __repr__(self): - receiving = "%08x " %self.rx.dword.dat + receiving = "{:08x} ".format(self.rx.dword.dat) receiving += decode_primitive(self.rx.dword.dat) receiving += " "*(16-len(receiving)) - sending = "%08x " %self.tx.dword.dat + sending = "{:08x} ".format(self.tx.dword.dat) sending += decode_primitive(self.tx.dword.dat) sending += " "*(16-len(sending)) @@ -115,7 +115,7 @@ class LinkRXPacket(LinkPacket): def check_crc(self): stdin = "" for v in self[:-1]: - stdin += "0x%08x " %v + stdin += "0x{:08x} ".format(v) stdin += "exit" with subprocess.Popen("./crc", stdin=subprocess.PIPE, stdout=subprocess.PIPE) as process: process.stdin.write(stdin.encode("ASCII")) @@ -134,7 +134,7 @@ class LinkTXPacket(LinkPacket): def insert_crc(self): stdin = "" for v in self: - stdin += "0x%08x " %v + stdin += "0x{:08x} ".foramt(v) stdin += "exit" with subprocess.Popen("./crc", stdin=subprocess.PIPE, stdout=subprocess.PIPE) as process: process.stdin.write(stdin.encode("ASCII")) @@ -313,7 +313,7 @@ class FIS: else: r = "<<<<<<<<\n" for k in sorted(self.description.keys()): - r += k + " : 0x%x" %getattr(self, k) + "\n" + r += k + " : 0x{:x}".format(getattr(self, k)) + "\n" return r @@ -362,7 +362,7 @@ class FIS_DATA(FIS): r = "FIS_DATA\n" r += FIS.__repr__(self) for data in self.packet[1:]: - r += "%08x\n" %data + r += "{:08x}\n".format(data) return r @@ -377,7 +377,7 @@ class FIS_UNKNOWN(FIS): else: r += "<<<<<<<<\n" for dword in self.packet: - r += "%08x\n" %dword + r += "{:08x}\n".format(dword) return r diff --git a/misoclib/mem/litesata/test/link_tb.py b/misoclib/mem/litesata/test/link_tb.py index 51142fb1..0790a0f4 100644 --- a/misoclib/mem/litesata/test/link_tb.py +++ b/misoclib/mem/litesata/test/link_tb.py @@ -44,7 +44,7 @@ class TB(Module): # check results s, l, e = check(streamer_packet, self.logger.packet) - print("shift "+ str(s) + " / length " + str(l) + " / errors " + str(e)) + print("shift " + str(s) + " / length " + str(l) + " / errors " + str(e)) if __name__ == "__main__": diff --git a/misoclib/mem/litesata/test/phy_datapath_tb.py b/misoclib/mem/litesata/test/phy_datapath_tb.py index 26557002..9b96d033 100644 --- a/misoclib/mem/litesata/test/phy_datapath_tb.py +++ b/misoclib/mem/litesata/test/phy_datapath_tb.py @@ -81,13 +81,13 @@ class TB(Module): yield from self.streamer.send(streamer_packet) yield from self.logger.receive(512) for d in self.logger.packet: - r = "%08x " %d - r +=decode_primitive(d) + r = "{:08x} ".format(d) + r += decode_primitive(d) print(r) # check results #s, l, e = check(streamer_packet, self.logger.packet) - #print("shift "+ str(s) + " / length " + str(l) + " / errors " + str(e)) + #print("shift " + str(s) + " / length " + str(l) + " / errors " + str(e)) if __name__ == "__main__": diff --git a/misoclib/mem/litesata/test/scrambler_tb.py b/misoclib/mem/litesata/test/scrambler_tb.py index 806c3e25..049ba353 100644 --- a/misoclib/mem/litesata/test/scrambler_tb.py +++ b/misoclib/mem/litesata/test/scrambler_tb.py @@ -12,7 +12,7 @@ class TB(Module): self.length = length def get_c_values(self, length): - stdin = "0x%08x" %length + stdin = "0x{:08x}".format(length) with subprocess.Popen("./scrambler", stdin=subprocess.PIPE, stdout=subprocess.PIPE) as process: process.stdin.write(stdin.encode("ASCII")) out, err = process.communicate() @@ -42,7 +42,7 @@ class TB(Module): # check results s, l, e = check(c_values, sim_values) - print("shift "+ str(s) + " / length " + str(l) + " / errors " + str(e)) + print("shift " + str(s) + " / length " + str(l) + " / errors " + str(e)) if __name__ == "__main__": from migen.sim.generic import run_simulation -- 2.30.2