From ea696be5ac097af621f10858d925a343a838be7a Mon Sep 17 00:00:00 2001 From: Kenneth Graunke Date: Wed, 25 Feb 2015 16:08:14 -0800 Subject: [PATCH] i965/fs: Patch the instruction generating discards; don't use CMP.Z. CMP.Z doesn't work on Gen4-5 because the boolean isn't guaranteed to be 0 or 0xFFFFFFFF - only the low bit is defined. We can call emit_bool_to_cond_code to generate the condition in f0.0; the last instruction will generate the flag value. We can patch it to use f0.1, and negate the condition. Fixes discard tests on Gen4-5. Haswell shader-db stats: total instructions in shared programs: 5770279 -> 5769112 (-0.02%) instructions in affected programs: 64342 -> 63175 (-1.81%) helped: 1069 Signed-off-by: Kenneth Graunke Reviewed-by: Matt Turner --- src/mesa/drivers/dri/i965/brw_fs_visitor.cpp | 5 +++-- 1 file changed, 3 insertions(+), 2 deletions(-) diff --git a/src/mesa/drivers/dri/i965/brw_fs_visitor.cpp b/src/mesa/drivers/dri/i965/brw_fs_visitor.cpp index 13a3bf29da8..7a697e898fe 100644 --- a/src/mesa/drivers/dri/i965/brw_fs_visitor.cpp +++ b/src/mesa/drivers/dri/i965/brw_fs_visitor.cpp @@ -2422,8 +2422,9 @@ fs_visitor::visit(ir_discard *ir) */ fs_inst *cmp; if (ir->condition) { - ir->condition->accept(this); - cmp = emit(CMP(reg_null_f, this->result, fs_reg(0), BRW_CONDITIONAL_Z)); + emit_bool_to_cond_code(ir->condition); + cmp = (fs_inst *) this->instructions.get_tail(); + cmp->conditional_mod = brw_negate_cmod(cmp->conditional_mod); } else { fs_reg some_reg = fs_reg(retype(brw_vec8_grf(0, 0), BRW_REGISTER_TYPE_UW)); -- 2.30.2