From ea8ab01b9912f8d5279f3771d43e6383a8a4b34c Mon Sep 17 00:00:00 2001 From: Cole Poirier Date: Fri, 21 Aug 2020 11:12:57 -0700 Subject: [PATCH] dcache.py fix asserts, use backslash and two strings, one per line, fixes rest of https://bugs.libre-soc.org/show_bug.cgi?id=469#c2 --- src/soc/experiment/dcache.py | 32 ++++++++++++++++---------------- 1 file changed, 16 insertions(+), 16 deletions(-) diff --git a/src/soc/experiment/dcache.py b/src/soc/experiment/dcache.py index e11ba0d6..9d833c40 100644 --- a/src/soc/experiment/dcache.py +++ b/src/soc/experiment/dcache.py @@ -1017,35 +1017,35 @@ class Dcache(Elaboratable): # assert SET_SIZE_BITS <= TLB_LG_PGSZ # report "Set indexed by virtual address" severity FAILURE; assert (LINE_SIZE % ROW_SIZE) == 0 "LINE_SIZE not " \ - "multiple of ROW_SIZE -!- severity FAILURE" + "multiple of ROW_SIZE -!- severity FAILURE" assert (LINE_SIZE % 2) == 0 "LINE_SIZE not power of" \ - "2 -!- severity FAILURE" + "2 -!- severity FAILURE" - assert (NUM_LINES % 2) == 0 "NUM_LINES not power of - 2 -!- severity FAILURE" + assert (NUM_LINES % 2) == 0 "NUM_LINES not power of" \ + "2 -!- severity FAILURE" - assert (ROW_PER_LINE % 2) == 0 "ROW_PER_LINE not - power of 2 -!- severity FAILURE" + assert (ROW_PER_LINE % 2) == 0 "ROW_PER_LINE not" \ + "power of 2 -!- severity FAILURE" - assert ROW_BITS == (INDEX_BITS + ROW_LINE_BITS) + assert ROW_BITS == (INDEX_BITS + ROW_LINE_BITS) \ "geometry bits don't add up -!- severity FAILURE" - assert (LINE_OFF_BITS = ROW_OFF_BITS + ROW_LINEBITS) + assert (LINE_OFF_BITS = ROW_OFF_BITS + ROW_LINEBITS) \ "geometry bits don't add up -!- severity FAILURE" - assert REAL_ADDR_BITS == (TAG_BITS + INDEX_BITS - + LINE_OFF_BITS) "geometry bits don't add up -!- - severity FAILURE" + assert REAL_ADDR_BITS == (TAG_BITS + INDEX_BITS \ + + LINE_OFF_BITS) "geometry bits don't add up -!-" \ + "severity FAILURE" - assert REAL_ADDR_BITS == (TAG_BITS + ROW_BITS + ROW_OFF_BITS) + assert REAL_ADDR_BITS == (TAG_BITS + ROW_BITS + ROW_OFF_BITS) \ "geometry bits don't add up -!- severity FAILURE" - assert 64 == wishbone_data_bits "Can't yet handle a - wishbone width that isn't 64-bits -!- severity FAILURE" + assert 64 == wishbone_data_bits "Can't yet handle a" \ + "wishbone width that isn't 64-bits -!- severity FAILURE" - assert SET_SIZE_BITS <= TLB_LG_PGSZ "Set indexed by - virtual address -!- severity FAILURE" + assert SET_SIZE_BITS <= TLB_LG_PGSZ "Set indexed by" \ + "virtual address -!- severity FAILURE" # -- Latch the request in r0.req as long as we're not stalling # stage_0 : process(clk) -- 2.30.2