From ea9be0775811e679b8c32cf11475ff4c432852fa Mon Sep 17 00:00:00 2001
From: Michael Meissner <meissner@gcc.gnu.org>
Date: Wed, 15 Mar 1995 20:01:18 +0000
Subject: [PATCH] Generate better code for sne on PowerPC.

From-SVN: r9184
---
 gcc/config/rs6000/rs6000.md | 62 ++++++++++++++++++++++++++++++++++++-
 1 file changed, 61 insertions(+), 1 deletion(-)

diff --git a/gcc/config/rs6000/rs6000.md b/gcc/config/rs6000/rs6000.md
index 40db7c6b8db..e546a5cb1cd 100644
--- a/gcc/config/rs6000/rs6000.md
+++ b/gcc/config/rs6000/rs6000.md
@@ -1020,18 +1020,67 @@
 
 ;; We don't need abs with condition code because such comparisons should
 ;; never be done.
-(define_insn "abssi2"
+(define_expand "abssi2"
+  [(set (match_operand:SI 0 "gpc_reg_operand" "")
+	(abs:SI (match_operand:SI 1 "gpc_reg_operand" "")))]
+  ""
+  "
+{
+  if (!TARGET_POWER)
+    {
+      emit_insn (gen_abssi2_nopower (operands[0], operands[1]));
+      DONE;
+    }
+}")
+
+(define_insn "abssi2_power"
   [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
 	(abs:SI (match_operand:SI 1 "gpc_reg_operand" "r")))]
   "TARGET_POWER"
   "abs %0,%1")
 
+(define_insn "abssi2_nopower"
+  [(set (match_operand:SI 0 "gpc_reg_operand" "=&r,r")
+	(abs:SI (match_operand:SI 1 "gpc_reg_operand" "r,0")))
+   (clobber (match_scratch:SI 2 "=&r,&r"))]
+  "!TARGET_POWER"
+  "{srai|srawi} %2,%1,31\;xor %0,%2,%1\;subf %0,%2,%0"
+  [(set_attr "length" "12")])
+
+(define_split
+  [(set (match_operand:SI 0 "gpc_reg_operand" "=&r,r")
+	(abs:SI (match_operand:SI 1 "gpc_reg_operand" "r,0")))
+   (clobber (match_scratch:SI 2 "=&r,&r"))]
+  "!TARGET_POWER && reload_completed"
+  [(set (match_dup 2) (ashiftrt:SI (match_dup 1) (const_int 31)))
+   (set (match_dup 0) (xor:SI (match_dup 2) (match_dup 1)))
+   (set (match_dup 0) (minus:SI (match_dup 2) (match_dup 0)))]
+  "")
+
 (define_insn ""
   [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
 	(neg:SI (abs:SI (match_operand:SI 1 "gpc_reg_operand" "r"))))]
   "TARGET_POWER"
   "nabs %0,%1")
 
+(define_insn ""
+  [(set (match_operand:SI 0 "gpc_reg_operand" "=&r,r")
+	(neg:SI (abs:SI (match_operand:SI 1 "gpc_reg_operand" "r,0"))))
+   (clobber (match_scratch:SI 2 "=&r,&r"))]
+  "!TARGET_POWER"
+  "{srai|srawi} %2,%1,31\;xor %0,%2,%1\;subf %0,%0,%2"
+  [(set_attr "length" "12")])
+
+(define_split
+  [(set (match_operand:SI 0 "gpc_reg_operand" "=&r,r")
+	(neg:SI (abs:SI (match_operand:SI 1 "gpc_reg_operand" "r,0"))))
+   (clobber (match_scratch:SI 2 "=&r,&r"))]
+  "!TARGET_POWER && reload_completed"
+  [(set (match_dup 2) (ashiftrt:SI (match_dup 1) (const_int 31)))
+   (set (match_dup 0) (xor:SI (match_dup 2) (match_dup 1)))
+   (set (match_dup 0) (minus:SI (match_dup 0) (match_dup 2)))]
+  "")
+
 (define_insn "negsi2"
   [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
 	(neg:SI (match_operand:SI 1 "gpc_reg_operand" "r")))]
@@ -5704,6 +5753,17 @@
    {sfi|subfic} %0,%1,%2\;{ai|addic} %0,%0,-1\;{sfe|subfe} %0,%0,%0"
    [(set_attr "length" "12,8,12,12,12")])
 
+;; Simplify (ne X (const_int 0)) on the PowerPC.  No need to on the Power,
+;; since it nabs/sr is just as fast.
+(define_insn ""
+  [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
+	(lshiftrt:SI (neg:SI (abs:SI (match_operand:SI 1 "gpc_reg_operand" "r")))
+		     (const_int 31)))
+   (clobber (match_scratch:SI 2 "=&r"))]
+  "!TARGET_POWER"
+  "{ai|addic} %2,%1,-1\;{sfe|subfe} %0,%2,%1"
+  [(set_attr "length" "8")])
+
 ;; This is what (plus (ne X (const_int 0)) Y) looks like.
 (define_insn ""
   [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
-- 
2.30.2