From ea9c1b8e69a672b2bcdc8243a49ca7854f6c95b0 Mon Sep 17 00:00:00 2001 From: Florent Kermarrec Date: Wed, 18 Mar 2015 14:58:40 +0100 Subject: [PATCH] fhdl/verilog: revert "fhdl/verilog: add simulation parameter to avoid simulation tricks in synthetizable code" This probably breaks simulation with Icarus Verilog (and others simulators?) --- mibuild/generic_platform.py | 4 ++-- migen/fhdl/verilog.py | 40 +++++++++++++++++-------------------- 2 files changed, 20 insertions(+), 24 deletions(-) diff --git a/mibuild/generic_platform.py b/mibuild/generic_platform.py index dca8de6c..4b4a6e3c 100644 --- a/mibuild/generic_platform.py +++ b/mibuild/generic_platform.py @@ -274,11 +274,11 @@ class GenericPlatform: def get_verilog(self, fragment, **kwargs): return self._get_source(fragment, lambda f: verilog.convert(f, self.constraint_manager.get_io_signals(), - return_ns=True, create_clock_domains=False, simulation=False, **kwargs)) + return_ns=True, create_clock_domains=False, **kwargs)) def get_edif(self, fragment, cell_library, vendor, device, **kwargs): return self._get_source(fragment, lambda f: edif.convert(f, self.constraint_manager.get_io_signals(), - cell_library, vendor, device, return_ns=True, simulation=False, **kwargs)) + cell_library, vendor, device, return_ns=True, **kwargs)) def build(self, fragment): raise NotImplementedError("GenericPlatform.build must be overloaded") diff --git a/migen/fhdl/verilog.py b/migen/fhdl/verilog.py index de36556f..b4bd534e 100644 --- a/migen/fhdl/verilog.py +++ b/migen/fhdl/verilog.py @@ -175,19 +175,18 @@ def _printheader(f, ios, name, ns): r += "\n" return r -def _printcomb(f, ns, simulation, display_run): +def _printcomb(f, ns, display_run): r = "" if f.comb: - if simulation: - # Generate a dummy event to get the simulator - # to run the combinatorial process once at the beginning. - syn_off = "// synthesis translate_off\n" - syn_on = "// synthesis translate_on\n" - dummy_s = Signal(name_override="dummy_s") - r += syn_off - r += "reg " + _printsig(ns, dummy_s) + ";\n" - r += "initial " + ns.get_name(dummy_s) + " <= 1'd0;\n" - r += syn_on + # Generate a dummy event to get the simulator + # to run the combinatorial process once at the beginning. + syn_off = "// synthesis translate_off\n" + syn_on = "// synthesis translate_on\n" + dummy_s = Signal(name_override="dummy_s") + r += syn_off + r += "reg " + _printsig(ns, dummy_s) + ";\n" + r += "initial " + ns.get_name(dummy_s) + " <= 1'd0;\n" + r += syn_on groups = group_by_targets(f.comb) @@ -195,11 +194,10 @@ def _printcomb(f, ns, simulation, display_run): if len(g[1]) == 1 and isinstance(g[1][0], _Assign): r += "assign " + _printnode(ns, _AT_BLOCKING, 0, g[1][0]) else: - if simulation: - dummy_d = Signal(name_override="dummy_d") - r += "\n" + syn_off - r += "reg " + _printsig(ns, dummy_d) + ";\n" - r += syn_on + dummy_d = Signal(name_override="dummy_d") + r += "\n" + syn_off + r += "reg " + _printsig(ns, dummy_d) + ";\n" + r += syn_on r += "always @(*) begin\n" if display_run: @@ -207,10 +205,9 @@ def _printcomb(f, ns, simulation, display_run): for t in g[0]: r += "\t" + ns.get_name(t) + " <= " + _printexpr(ns, t.reset)[0] + ";\n" r += _printnode(ns, _AT_NONBLOCKING, 1, g[1]) - if simulation: - r += syn_off - r += "\t" + ns.get_name(dummy_d) + " <= " + ns.get_name(dummy_s) + ";\n" - r += syn_on + r += syn_off + r += "\t" + ns.get_name(dummy_d) + " <= " + ns.get_name(dummy_s) + ";\n" + r += syn_on r += "end\n" r += "\n" return r @@ -290,7 +287,6 @@ def convert(f, ios=None, name="top", return_ns=False, special_overrides=dict(), create_clock_domains=True, - simulation=True, display_run=False): if not isinstance(f, _Fragment): f = f.get_fragment() @@ -320,7 +316,7 @@ def convert(f, ios=None, name="top", r = "/* Machine-generated using Migen */\n" r += _printheader(f, ios, name, ns) - r += _printcomb(f, ns, simulation, display_run) + r += _printcomb(f, ns, display_run) r += _printsync(f, ns) r += _printspecials(special_overrides, f.specials - lowered_specials, ns) r += _printinit(f, ios, ns) -- 2.30.2