From eaaef09c04560c5259079d53519ebefc8164369f Mon Sep 17 00:00:00 2001 From: Luke Kenneth Casson Leighton Date: Mon, 27 Mar 2023 12:20:32 +0100 Subject: [PATCH] mention that svshape2 sits within svshape --- openpower/sv/rfc/ls009.mdwn | 23 +++++++++++++++++++++-- 1 file changed, 21 insertions(+), 2 deletions(-) diff --git a/openpower/sv/rfc/ls009.mdwn b/openpower/sv/rfc/ls009.mdwn index b3bea0d17..1962e726d 100644 --- a/openpower/sv/rfc/ls009.mdwn +++ b/openpower/sv/rfc/ls009.mdwn @@ -1020,7 +1020,7 @@ Fields: *Note: SVxd, SVyz and SVzd are all stored "off-by-one". In the assembler mnemonic the values `1-32` are stored in binary as `0b00000..0b11111`* -There are 14 REMAP Modes (2 bits are RESERVED for `svshape2`) +There are 14 REMAP Modes (2 Modes are RESERVED for `svshape2`) | SVRM | Remap Mode description | | -- | -- | @@ -1056,6 +1056,14 @@ to SVSHAPE0-3 with `mtspr`. Circumstances include Matrices with dimensions larger than 32, and in-place Transpose. Potentially a future v3.1 Prefixed instruction, `psvshape`, may extend the capability here. +*Architectural Resource Allocation note: the SVRM field is carefully +crafted to allocate two Modes, corresponding to bits 21-23 within the +instruction being set to the value `0b100`, to `svshape2` (not +`svshape`). These two Modes are +considered "RESERVED" within the context of `svshape` but it is +absolutely critical to allocate the exact same pattern in XO for +both instructions in bits 26-31.* + ------------- \newpage{} @@ -1378,13 +1386,19 @@ SPRs and those instructions are still in-flight then this position is clearly **invalid**. This is why Programmers are strongly discouraged from directly writing to these SPRs.* +*Architectural Resource Allocation note: this instruction shares +the space of `svshape`. Therefore it is critical that the two +instructions, `svshape` and `svshape2` have the exact same XO +in bits 26 thru 31. It is also critical that for `svshape2`, +bit 21 of XO is a 1, bit 22 of XO is a 0, and bit 23 of XO is a 0.* + ------------- \newpage{} # Forms -Add `SVI, SVM, SVM2, SVRM` to `XO (26:31)` Field in Book I, 1.6.2 +Add `SVI, SVM, SVRM` to `XO (26:31)` Field in Book I, 1.6.2 Add the following to Book I, 1.6.1, SVI-Form @@ -1480,6 +1494,11 @@ Add the following to Book I, 1.6.2 SVzd (16:20) Simple-V "REMAP" z-dimension size Formats: SVM + XO (21:23,26:31) + Extended opcode field. Note that bit 21 must be 1, 22 and 23 + must be zero, and bits 26-31 must be exactly the same as + used for svshape. + Formats: SVM2 ``` # Appendices -- 2.30.2