From ead4a3f157e7989724161a0a510dca58b0678c74 Mon Sep 17 00:00:00 2001 From: Michael Meissner Date: Wed, 11 Sep 1996 20:54:21 +0000 Subject: [PATCH] Add tracing support; Fix some problems with hardwired sizes --- sim/v850/ChangeLog | 23 ++ sim/v850/configure.in | 13 + sim/v850/interp.c | 29 +- sim/v850/simops.c | 691 ++++++++++++++++++++++++++++++++++++------ 4 files changed, 650 insertions(+), 106 deletions(-) diff --git a/sim/v850/ChangeLog b/sim/v850/ChangeLog index 771b6d8db2e..a4bffb538ba 100644 --- a/sim/v850/ChangeLog +++ b/sim/v850/ChangeLog @@ -1,3 +1,26 @@ +Wed Sep 11 16:44:37 1996 Michael Meissner + + * simops.c: Add tracing support. Use SEXTxx macros instead of + doing hardwired shifts. + + * configure.in (--enable-sim-cflags): Add switch to add additional + flags to simulator buld. If --enable-sim-cflags=trace, turn on + tracing. + * configure: Regenerate. + + * Makefile.in: Don't require a VPATH capable make if configuring + in the same directory. Don't use CFLAGS for configuration flags. + Add flags from --enable-sim-cflags. Support canadian cross + builds. Rebuild whole simulator if include files change. + + * interp.c (v850_debug): New global for debugging. + (lookup_hash,sim_size,sim_set_profile): Use + printf_filtered callback, instead of calling printf directly. + (sim_{open,trace}): Enable tracing if -t and compiled for tracing. + + * v850_sim.h: Use limits.h to set the various sized types. + (SEXT{5,7,16,22}): New macros. + Mon Sep 9 20:50:46 1996 Jeffrey A Law (law@cygnus.com) * interp.c (hash): Make this an inline function diff --git a/sim/v850/configure.in b/sim/v850/configure.in index 6bc9b3ccf5e..cd1700a1b8b 100644 --- a/sim/v850/configure.in +++ b/sim/v850/configure.in @@ -11,11 +11,24 @@ AC_C_BIGENDIAN . ${srcdir}/../../bfd/configure.host +AC_ARG_ENABLE(sim-cflags, +[ --enable-sim-cflags=opts Extra CFLAGS for use in building simulator], +[case "${enableval}" in + yes) sim_cflags="-O2";; + trace) sim_cflags="-O2 -DDEBUG=3";; + no) sim_cflags="";; + *) sim_cflags=`echo "${enableval}" | sed -e "s/,/ /g"`;; +esac +if test x"$silent" != x"yes" && test x"$sim_cflags" != x""; then + echo "Setting sim cflags = $sim_cflags" 6>&1 +fi],[sim_cflags=""])dnl + AC_SUBST(CFLAGS) AC_SUBST(HDEFINES) AR=${AR-ar} AC_SUBST(AR) AC_PROG_RANLIB +AC_SUBST(sim_cflags) # Put a plausible default for CC_FOR_BUILD in Makefile. AC_C_CROSS diff --git a/sim/v850/interp.c b/sim/v850/interp.c index b9f5a9edc4c..ce707432e88 100644 --- a/sim/v850/interp.c +++ b/sim/v850/interp.c @@ -17,6 +17,7 @@ #define MEM_SIZE 18 /* V850 memory size is 18 bits XXX */ host_callback *v850_callback; +int v850_debug; uint32 OP[4]; @@ -75,7 +76,7 @@ lookup_hash (ins) { if (h->next == NULL) { - printf ("ERROR looking up hash for %x\n",ins); + (*v850_callback->printf_filtered) (v850_callback, "ERROR looking up hash for %x\n", ins); exit(1); } h = h->next; @@ -248,7 +249,7 @@ sim_size (power) State.mem = (uint8 *)calloc(1,1<printf_filtered) (v850_callback, "Memory allocation failed.\n"); exit(1); } } @@ -283,7 +284,14 @@ sim_open (args) struct simops *s; struct hash_entry *h; if (args != NULL) - printf ("sim_open %s\n",args); + { +#ifdef DEBUG + if (strcmp (args, "-t") == 0) + d10v_debug = DEBUG; + else +#endif + (*d10v_callback->printf_filtered) (d10v_callback, "ERROR: unsupported option(s): %s\n",args); + } /* put all the opcodes in the hash table */ for (s = Simops; s->func; s++) @@ -317,14 +325,14 @@ void sim_set_profile (n) int n; { - printf ("sim_set_profile %d\n",n); + (*v850_callback->printf_filtered) (v850_callback, "sim_set_profile %d\n", n); } void sim_set_profile_size (n) int n; { - printf ("sim_set_profile_size %d\n",n); + (*v850_callback->printf_filtered) (v850_callback, "sim_set_profile_size %d\n", n); } void @@ -396,15 +404,18 @@ sim_resume (step, siggnal) int sim_trace () { - printf ("sim_trace\n"); - return 0; +#ifdef DEBUG + v850_debug = DEBUG; +#endif + sim_resume (0, 0); + return 1; } void sim_info (verbose) int verbose; { - printf ("sim_info\n"); + (*v850_callback->printf_filtered) (v850_callback, "sim_info\n"); } void @@ -480,7 +491,7 @@ void sim_do_command (cmd) char *cmd; { - printf("sim_do_command: %s\n",cmd); + (*v850_callback->printf_filtered) (v850_callback, "sim_do_command: %s\n", cmd); } int diff --git a/sim/v850/simops.c b/sim/v850/simops.c index 2c47db80bbe..215ba56e2b1 100644 --- a/sim/v850/simops.c +++ b/sim/v850/simops.c @@ -3,6 +3,355 @@ #include "simops.h" #include "sys/syscall.h" +enum op_types { + OP_UNKNOWN, + OP_NONE, + OP_TRAP, + OP_REG, + OP_REG_REG, + OP_REG_REG_CMP, + OP_REG_REG_MOVE, + OP_IMM_REG, + OP_IMM_REG_CMP, + OP_IMM_REG_MOVE, + OP_COND_BR, + OP_LOAD16, + OP_STORE16, + OP_LOAD32, + OP_STORE32, + OP_JUMP, + OP_IMM_REG_REG, + OP_UIMM_REG_REG, + OP_BIT, + OP_EX1, + OP_EX2, + OP_LDSR, + OP_STSR +}; + +#ifdef DEBUG +static void trace_input PARAMS ((char *name, enum op_types type, int size)); +static void trace_output PARAMS ((enum op_types result)); + +#ifndef SIZE_INSTRUCTION +#define SIZE_INSTRUCTION 6 +#endif + +#ifndef SIZE_OPERANDS +#define SIZE_OPERANDS 16 +#endif + +#ifndef SIZE_VALUES +#define SIZE_VALUES 11 +#endif + +static void +trace_input (name, type, size) + char *name; + enum op_types type; + int size; +{ + char buf[80]; + uint32 values[3]; + int num_values, i; + char *cond; + + if ((v850_debug & DEBUG_TRACE) == 0) + return; + + (*v850_callback->printf_filtered) (v850_callback, + "0x%.8x: %-*s", + (unsigned)PC, + SIZE_INSTRUCTION, name); + + switch (type) + { + default: + case OP_UNKNOWN: + case OP_NONE: + strcpy (buf, "unknown"); + break; + + case OP_TRAP: + sprintf (buf, "%d", OP[0]); + break; + + case OP_REG: + sprintf (buf, "r%d", OP[0]); + break; + + case OP_REG_REG: + case OP_REG_REG_CMP: + case OP_REG_REG_MOVE: + sprintf (buf, "r%d,r%d", OP[0], OP[1]); + break; + + case OP_IMM_REG: + case OP_IMM_REG_CMP: + case OP_IMM_REG_MOVE: + sprintf (buf, "%d,r%d", OP[1], OP[0]); + break; + + case OP_COND_BR: + sprintf (buf, "%d", SEXT9 (OP[0])); + break; + + case OP_LOAD16: + sprintf (buf, "%d[r30],r%d", SEXT7 (OP[1]) * size, OP[0]); + break; + + case OP_STORE16: + sprintf (buf, "r%d,%d[r30]", OP[0], SEXT7 (OP[1]) * size); + break; + + case OP_LOAD32: + sprintf (buf, "%d[r%d],r%d", SEXT16 (OP[2]), OP[0], OP[1]); + break; + + case OP_STORE32: + sprintf (buf, "r%d,%d[r%d]", OP[1], SEXT16 (OP[2]), OP[0]); + break; + + case OP_JUMP: + sprintf (buf, "%d,r%d", SEXT22 (OP[0]), OP[1]); + break; + + case OP_IMM_REG_REG: + sprintf (buf, "%d,r%d,r%d", SEXT16 (OP[0]), OP[1], OP[2]); + break; + + case OP_UIMM_REG_REG: + sprintf (buf, "%d,r%d,r%d", OP[0] & 0xffff, OP[1], OP[2]); + break; + + case OP_BIT: + sprintf (buf, "%d,%d[r%d]", OP[1] & 0x7, SEXT16 (OP[2]), OP[0]); + break; + + case OP_EX1: + switch (OP[0] & 0xf) + { + default: cond = "?"; break; + case 0x0: cond = "v"; break; + case 0x1: cond = "c"; break; + case 0x2: cond = "z"; break; + case 0x3: cond = "nh"; break; + case 0x4: cond = "s"; break; + case 0x5: cond = "t"; break; + case 0x6: cond = "lt"; break; + case 0x7: cond = "le"; break; + case 0x8: cond = "nv"; break; + case 0x9: cond = "nc"; break; + case 0xa: cond = "nz"; break; + case 0xb: cond = "h"; break; + case 0xc: cond = "ns"; break; + case 0xd: cond = "sa"; break; + case 0xe: cond = "ge"; break; + case 0xf: cond = "gt"; break; + } + + sprintf (buf, "%s,r%d", cond, OP[1]); + break; + + case OP_EX2: + strcpy (buf, "EX2"); + break; + + case OP_LDSR: + case OP_STSR: + sprintf (buf, "r%d,s%d", OP[0], OP[1]); + break; + } + + if ((v850_debug & DEBUG_VALUES) == 0) + { + (*v850_callback->printf_filtered) (v850_callback, "%s\n", buf); + } + else + { + (*v850_callback->printf_filtered) (v850_callback, "%-*s", SIZE_OPERANDS, buf); + switch (type) + { + default: + case OP_UNKNOWN: + case OP_NONE: + case OP_TRAP: + num_values = 0; + break; + + case OP_REG: + case OP_REG_REG_MOVE: + values[0] = State.regs[OP[0]]; + num_values = 1; + break; + + case OP_REG_REG: + case OP_REG_REG_CMP: + values[0] = State.regs[OP[1]]; + values[1] = State.regs[OP[0]]; + num_values = 2; + break; + + case OP_IMM_REG: + case OP_IMM_REG_CMP: + values[0] = SEXT5 (OP[0]); + values[1] = OP[1]; + num_values = 2; + break; + + case OP_IMM_REG_MOVE: + values[0] = SEXT5 (OP[0]); + num_values = 1; + break; + + case OP_COND_BR: + values[0] = State.pc; + values[1] = SEXT9 (OP[0]); + values[2] = State.sregs[5]; + num_values = 3; + break; + + case OP_LOAD16: + values[0] = SEXT7 (OP[1]) * size; + values[1] = State.regs[30]; + num_values = 2; + break; + + case OP_STORE16: + values[0] = State.regs[OP[0]]; + values[1] = SEXT7 (OP[1]) * size; + values[2] = State.regs[30]; + num_values = 3; + break; + + case OP_LOAD32: + values[0] = SEXT16 (OP[2]); + values[1] = State.regs[OP[0]]; + num_values = 2; + break; + + case OP_STORE32: + values[0] = State.regs[OP[1]]; + values[1] = SEXT16 (OP[2]); + values[2] = State.regs[OP[0]]; + num_values = 3; + break; + + case OP_JUMP: + values[0] = SEXT22 (OP[0]); + values[1] = State.pc; + num_values = 2; + break; + + case OP_IMM_REG_REG: + values[0] = SEXT16 (OP[0]) << size; + values[1] = State.regs[OP[1]]; + num_values = 2; + break; + + case OP_UIMM_REG_REG: + values[0] = (OP[0] & 0xffff) << size; + values[1] = State.regs[OP[1]]; + num_values = 2; + break; + + case OP_BIT: + num_values = 0; + break; + + case OP_EX1: + values[0] = State.sregs[5]; + num_values = 1; + break; + + case OP_EX2: + num_values = 0; + break; + + case OP_LDSR: + values[0] = State.regs[OP[0]]; + num_values = 1; + break; + + case OP_STSR: + values[0] = State.sregs[OP[1]]; + num_values = 1; + } + + for (i = 0; i < num_values; i++) + (*v850_callback->printf_filtered) (v850_callback, "%*s0x%.8lx", SIZE_VALUES - 10, "", values[i]); + + while (i++ < 3) + (*v850_callback->printf_filtered) (v850_callback, "%*s", SIZE_VALUES, ""); + } +} + +static void +trace_output (result) + enum op_types result; +{ + if ((v850_debug & (DEBUG_TRACE | DEBUG_VALUES)) == (DEBUG_TRACE | DEBUG_VALUES)) + { + switch (result) + { + default: + case OP_UNKNOWN: + case OP_NONE: + case OP_TRAP: + case OP_REG: + case OP_REG_REG_CMP: + case OP_IMM_REG_CMP: + case OP_COND_BR: + case OP_STORE16: + case OP_STORE32: + case OP_BIT: + case OP_EX2: + break; + + case OP_LOAD16: + case OP_STSR: + (*v850_callback->printf_filtered) (v850_callback, " :: 0x%.8lx", + (unsigned long)State.regs[OP[0]]); + break; + + case OP_REG_REG: + case OP_REG_REG_MOVE: + case OP_IMM_REG: + case OP_IMM_REG_MOVE: + case OP_LOAD32: + case OP_EX1: + (*v850_callback->printf_filtered) (v850_callback, " :: 0x%.8lx", + (unsigned long)State.regs[OP[1]]); + break; + + case OP_IMM_REG_REG: + case OP_UIMM_REG_REG: + (*v850_callback->printf_filtered) (v850_callback, " :: 0x%.8lx", + (unsigned long)State.regs[OP[2]]); + break; + + case OP_JUMP: + if (OP[1] != 0) + (*v850_callback->printf_filtered) (v850_callback, " :: 0x%.8lx", + (unsigned long)State.regs[OP[1]]); + break; + + case OP_LDSR: + (*v850_callback->printf_filtered) (v850_callback, " :: 0x%.8lx", + (unsigned long)State.sregs[OP[1]]); + break; + } + + (*v850_callback->printf_filtered) (v850_callback, "\n"); + } +} + +#else +#define trace_input(NAME, IN1, IN2, IN3) +#define trace_output(RESULT) +#endif + + /* sld.b */ void OP_300 () @@ -10,12 +359,13 @@ OP_300 () unsigned int op2; int result, temp; + trace_input ("sld.b", OP_LOAD16, 1); temp = OP[1]; - temp = (temp << 25) >> 25; + temp = SEXT7 (temp); op2 = temp; result = get_byte (State.mem + State.regs[30] + op2); - result = (result << 24) >> 24; - State.regs[OP[0]] = result; + State.regs[OP[0]] = SEXT8 (result); + trace_output (OP_LOAD16); } /* sld.h */ @@ -25,12 +375,13 @@ OP_400 () unsigned int op2; int result, temp; + trace_input ("sld.h", OP_LOAD16, 2); temp = OP[1]; - temp = (temp << 25) >> 25; + temp = SEXT7 (temp); op2 = temp << 1; result = get_half (State.mem + State.regs[30] + op2); - result = (result << 16) >> 16; - State.regs[OP[0]] = result; + State.regs[OP[0]] = SEXT16 (result); + trace_output (OP_LOAD16); } /* sld.w */ @@ -40,11 +391,13 @@ OP_500 () unsigned int op2; int result, temp; + trace_input ("sld.w", OP_LOAD16, 4); temp = OP[1]; - temp = (temp << 25) >> 25; + temp = SEXT7 (temp); op2 = temp << 2; result = get_word (State.mem + State.regs[30] + op2); State.regs[OP[0]] = result; + trace_output (OP_LOAD16); } /* sst.b */ @@ -54,11 +407,13 @@ OP_380 () unsigned int op0, op1; int temp; + trace_input ("sst.b", OP_STORE16, 1); op0 = State.regs[OP[0]]; temp = OP[1]; - temp = (temp << 25) >> 25; + temp = SEXT7 (temp); op1 = temp; put_byte (State.mem + State.regs[30] + op1, op0); + trace_output (OP_STORE16); } /* sst.h */ @@ -68,11 +423,13 @@ OP_480 () unsigned int op0, op1; int temp; + trace_input ("sst.h", OP_STORE16, 2); op0 = State.regs[OP[0]]; temp = OP[1]; - temp = (temp << 25) >> 25; + temp = SEXT7 (temp); op1 = temp << 1; put_half (State.mem + State.regs[30] + op1, op0); + trace_output (OP_STORE16); } /* sst.w */ @@ -82,11 +439,13 @@ OP_501 () unsigned int op0, op1; int temp; + trace_input ("sst.w", OP_STORE16, 4); op0 = State.regs[OP[0]]; temp = OP[1]; - temp = (temp << 25) >> 25; + temp = SEXT7 (temp); op1 = temp << 2; put_word (State.mem + State.regs[30] + op1, op0); + trace_output (OP_STORE16); } /* ld.b */ @@ -96,13 +455,13 @@ OP_700 () unsigned int op0, op2; int result, temp; + trace_input ("ld.b", OP_LOAD32, 1); op0 = State.regs[OP[0]]; - temp = OP[2]; - temp = (temp << 16) >> 16; + temp = SEXT16 (OP[2]); op2 = temp; result = get_byte (State.mem + op0 + op2); - result = (result << 24) >> 24; - State.regs[OP[1]] = result; + State.regs[OP[1]] = SEXT8 (result); + trace_output (OP_LOAD32); } /* ld.h */ @@ -112,14 +471,14 @@ OP_720 () unsigned int op0, op2; int result, temp; + trace_input ("ld.h", OP_LOAD32, 2); op0 = State.regs[OP[0]]; - temp = OP[2]; - temp = (temp << 16) >> 16; + temp = SEXT16 (OP[2]); temp &= ~0x1; op2 = temp; result = get_half (State.mem + op0 + op2); - result = (result << 16) >> 16; - State.regs[OP[1]] = result; + State.regs[OP[1]] = SEXT16 (result); + trace_output (OP_LOAD32); } /* ld.w */ @@ -129,13 +488,14 @@ OP_10720 () unsigned int op0, op2; int result, temp; + trace_input ("ld.w", OP_LOAD32, 4); op0 = State.regs[OP[0]]; - temp = OP[2]; - temp = (temp << 16) >> 16; + temp = SEXT16 (OP[2]); temp &= ~0x1; op2 = temp; result = get_word (State.mem + op0 + op2); State.regs[OP[1]] = result; + trace_output (OP_LOAD32); } /* st.b */ @@ -145,12 +505,13 @@ OP_740 () unsigned int op0, op1, op2; int temp; + trace_input ("st.b", OP_STORE32, 1); op0 = State.regs[OP[0]]; op1 = State.regs[OP[1]]; - temp = OP[2]; - temp = (temp << 16) >> 16; + temp = SEXT16 (OP[2]); op2 = temp; put_byte (State.mem + op0 + op2, op1); + trace_output (OP_STORE32); } /* st.h */ @@ -160,13 +521,13 @@ OP_760 () unsigned int op0, op1, op2; int temp; + trace_input ("st.h", OP_STORE32, 2); op0 = State.regs[OP[0]]; op1 = State.regs[OP[1]]; - temp = OP[2]; - temp &= ~0x1; - temp = (temp << 16) >> 16; + temp = SEXT16 (OP[2] & ~0x1); op2 = temp; put_half (State.mem + op0 + op2, op1); + trace_output (OP_STORE32); } /* st.w */ @@ -176,122 +537,145 @@ OP_10760 () unsigned int op0, op1, op2; int temp; + trace_input ("st.w", OP_STORE32, 4); op0 = State.regs[OP[0]]; op1 = State.regs[OP[1]]; - temp = OP[2]; - temp &= ~0x1; - temp = (temp << 16) >> 16; + temp = SEXT16 (OP[2] & ~0x1); op2 = temp; put_word (State.mem + op0 + op2, op1); + trace_output (OP_STORE32); } /* bv disp9 */ void OP_580 () { - unsigned int op0, psw; + unsigned int psw; + int op0; - op0 = ((signed)OP[0] << 23) >> 23; + trace_input ("bv", OP_COND_BR, 0); + op0 = SEXT9 (OP[0]); psw = State.sregs[5]; if ((psw & PSW_OV) != 0) State.pc += op0; else State.pc += 2; + trace_output (OP_COND_BR); } /* bl disp9 */ void OP_581 () { - unsigned int op0, psw; + unsigned int psw; + int op0; - op0 = ((signed)OP[0] << 23) >> 23; + trace_input ("bl", OP_COND_BR, 0); + op0 = SEXT9 (OP[0]); psw = State.sregs[5]; if ((psw & PSW_CY) != 0) State.pc += op0; else State.pc += 2; + trace_output (OP_COND_BR); } /* be disp9 */ void OP_582 () { - unsigned int op0, psw; + unsigned int psw; + int op0; - op0 = ((signed)OP[0] << 23) >> 23; + trace_input ("be", OP_COND_BR, 0); + op0 = SEXT9 (OP[0]); psw = State.sregs[5]; if ((psw & PSW_Z) != 0) State.pc += op0; else State.pc += 2; + trace_output (OP_COND_BR); } /* bnh disp 9*/ void OP_583 () { - unsigned int op0, psw; + unsigned int psw; + int op0; - op0 = ((signed)OP[0] << 23) >> 23; + trace_input ("bnh", OP_COND_BR, 0); + op0 = SEXT9 (OP[0]); psw = State.sregs[5]; if ((((psw & PSW_CY) != 0) | ((psw & PSW_Z) != 0)) != 0) State.pc += op0; else State.pc += 2; + trace_output (OP_COND_BR); } /* bn disp9 */ void OP_584 () { - unsigned int op0, psw; + unsigned int psw; + int op0; - op0 = ((signed)OP[0] << 23) >> 23; + trace_input ("bn", OP_COND_BR, 0); + op0 = SEXT9 (OP[0]); psw = State.sregs[5]; if ((psw & PSW_S) != 0) State.pc += op0; else State.pc += 2; + trace_output (OP_COND_BR); } /* br disp9 */ void OP_585 () { - unsigned int op0; + unsigned int psw; + int op0; - op0 = ((signed)OP[0] << 23) >> 23; + trace_input ("br", OP_COND_BR, 0); + op0 = SEXT9 (OP[0]); State.pc += op0; + trace_output (OP_COND_BR); } /* blt disp9 */ void OP_586 () { - unsigned int op0, psw; + unsigned int psw; + int op0; - op0 = ((signed)OP[0] << 23) >> 23; + trace_input ("blt", OP_COND_BR, 0); + op0 = SEXT9 (OP[0]); psw = State.sregs[5]; if ((((psw & PSW_S) != 0) ^ ((psw & PSW_OV) != 0)) != 0) State.pc += op0; else State.pc += 2; + trace_output (OP_COND_BR); } /* ble disp9 */ void OP_587 () { - unsigned int op0, psw; + unsigned int psw; + int op0; - op0 = ((signed)OP[0] << 23) >> 23; + trace_input ("ble", OP_COND_BR, 0); + op0 = SEXT9 (OP[0]); psw = State.sregs[5]; if ((((psw & PSW_Z) != 0) @@ -299,120 +683,144 @@ OP_587 () State.pc += op0; else State.pc += 2; + trace_output (OP_COND_BR); } /* bnv disp9 */ void OP_588 () { - unsigned int op0, psw; + unsigned int psw; + int op0; - op0 = ((signed)OP[0] << 23) >> 23; + trace_input ("bnv", OP_COND_BR, 0); + op0 = SEXT9 (OP[0]); psw = State.sregs[5]; if ((psw & PSW_OV) == 0) State.pc += op0; else State.pc += 2; + trace_output (OP_COND_BR); } /* bnl disp9 */ void OP_589 () { - unsigned int op0, psw; + unsigned int psw; + int op0; - op0 = ((signed)OP[0] << 23) >> 23; + trace_input ("bnl", OP_COND_BR, 0); + op0 = SEXT9 (OP[0]); psw = State.sregs[5]; if ((psw & PSW_CY) == 0) State.pc += op0; else State.pc += 2; + trace_output (OP_COND_BR); } /* bne disp9 */ void OP_58A () { - unsigned int op0, psw; + unsigned int psw; + int op0; - op0 = ((signed)OP[0] << 23) >> 23; + trace_input ("bne", OP_COND_BR, 0); + op0 = SEXT9 (OP[0]); psw = State.sregs[5]; if ((psw & PSW_Z) == 0) State.pc += op0; else State.pc += 2; + trace_output (OP_COND_BR); } /* bh disp9 */ void OP_58B () { - unsigned int op0, psw; + unsigned int psw; + int op0; - op0 = ((signed)OP[0] << 23) >> 23; + trace_input ("bh", OP_COND_BR, 0); + op0 = SEXT9 (OP[0]); psw = State.sregs[5]; if ((((psw & PSW_CY) != 0) | ((psw & PSW_Z) != 0)) == 0) State.pc += op0; else State.pc += 2; + trace_output (OP_COND_BR); } /* bp disp9 */ void OP_58C () { - unsigned int op0, psw; + unsigned int psw; + int op0; - op0 = ((signed)OP[0] << 23) >> 23; + trace_input ("bp", OP_COND_BR, 0); + op0 = SEXT9 (OP[0]); psw = State.sregs[5]; if ((psw & PSW_S) == 0) State.pc += op0; else State.pc += 2; + trace_output (OP_COND_BR); } /* bsa disp9 */ void OP_58D () { - unsigned int op0, psw; + unsigned int psw; + int op0; - op0 = ((signed)OP[0] << 23) >> 23; + trace_input ("bsa", OP_COND_BR, 0); + op0 = SEXT9 (OP[0]); psw = State.sregs[5]; if ((psw & PSW_SAT) != 0) State.pc += op0; else State.pc += 2; + trace_output (OP_COND_BR); } /* bge disp9 */ void OP_58E () { - unsigned int op0, psw; + unsigned int psw; + int op0; - op0 = ((signed)OP[0] << 23) >> 23; + trace_input ("bge", OP_COND_BR, 0); + op0 = SEXT9 (OP[0]); psw = State.sregs[5]; if ((((psw & PSW_S) != 0) ^ ((psw & PSW_OV) != 0)) == 0) State.pc += op0; else State.pc += 2; + trace_output (OP_COND_BR); } /* bgt disp9 */ void OP_58F () { - unsigned int op0, psw; + unsigned int psw; + int op0; - op0 = ((signed)OP[0] << 23) >> 23; + trace_input ("bgt", OP_COND_BR, 0); + op0 = SEXT9 (OP[0]); psw = State.sregs[5]; if ((((psw & PSW_Z) != 0) @@ -420,6 +828,7 @@ OP_58F () State.pc += op0; else State.pc += 2; + trace_output (OP_COND_BR); } /* jmp [reg1] */ @@ -427,7 +836,9 @@ void OP_60 () { /* interp.c will bump this by +2, so correct for it here. */ + trace_input ("jmp", OP_REG, 0); State.pc = State.regs[OP[0]] - 2; + trace_output (OP_REG); } /* jarl disp22, reg */ @@ -437,8 +848,8 @@ OP_780 () unsigned int op0, opc; int temp; - temp = OP[0]; - temp = (temp << 10) >> 10; + trace_input ("jarl", OP_JUMP, 0); + temp = SEXT22 (OP[0]); op0 = temp; opc = State.pc; @@ -447,6 +858,7 @@ OP_780 () /* Gross. jarl X,r0 is really jr and doesn't save its result. */ if (OP[1] != 0) State.regs[OP[1]] = opc + 4; + trace_output (OP_JUMP); } /* add reg, reg */ @@ -455,6 +867,7 @@ OP_1C0 () { unsigned int op0, op1, result, z, s, cy, ov; + trace_input ("add", OP_REG_REG, 0); /* Compute the result. */ op0 = State.regs[OP[0]]; op1 = State.regs[OP[1]]; @@ -472,6 +885,7 @@ OP_1C0 () State.sregs[5] &= ~(PSW_Z | PSW_S | PSW_CY | PSW_OV); State.sregs[5] |= ((z ? PSW_Z : 0) | (s ? PSW_S : 0) | (cy ? PSW_CY : 0) | (ov ? PSW_OV : 0)); + trace_output (OP_REG_REG); } /* add sign_extend(imm5), reg */ @@ -481,9 +895,10 @@ OP_240 () unsigned int op0, op1, result, z, s, cy, ov; int temp; + trace_input ("add", OP_IMM_REG, 0); + /* Compute the result. */ - temp = (OP[0] & 0x1f); - temp = (temp << 27) >> 27; + temp = SEXT5 (OP[0]); op0 = temp; op1 = State.regs[OP[1]]; result = op0 + op1; @@ -500,6 +915,7 @@ OP_240 () State.sregs[5] &= ~(PSW_Z | PSW_S | PSW_CY | PSW_OV); State.sregs[5] |= ((z ? PSW_Z : 0) | (s ? PSW_S : 0) | (cy ? PSW_CY : 0) | (ov ? PSW_OV : 0)); + trace_output (OP_IMM_REG); } /* addi sign_extend(imm16), reg, reg */ @@ -509,9 +925,10 @@ OP_600 () unsigned int op0, op1, result, z, s, cy, ov; int temp; + trace_input ("addi", OP_IMM_REG_REG, 0); + /* Compute the result. */ - temp = (OP[0] & 0xffff); - temp = (temp << 16) >> 16; + temp = SEXT16 (OP[0]); op0 = temp; op1 = State.regs[OP[1]]; result = op0 + op1; @@ -528,6 +945,7 @@ OP_600 () State.sregs[5] &= ~(PSW_Z | PSW_S | PSW_CY | PSW_OV); State.sregs[5] |= ((z ? PSW_Z : 0) | (s ? PSW_S : 0) | (cy ? PSW_CY : 0) | (ov ? PSW_OV : 0)); + trace_output (OP_IMM_REG_REG); } /* sub reg1, reg2 */ @@ -536,6 +954,7 @@ OP_1A0 () { unsigned int op0, op1, result, z, s, cy, ov; + trace_input ("sub", OP_REG_REG, 0); /* Compute the result. */ op0 = State.regs[OP[0]]; op1 = State.regs[OP[1]]; @@ -553,6 +972,7 @@ OP_1A0 () State.sregs[5] &= ~(PSW_Z | PSW_S | PSW_CY | PSW_OV); State.sregs[5] |= ((z ? PSW_Z : 0) | (s ? PSW_S : 0) | (cy ? PSW_CY : 0) | (ov ? PSW_OV : 0)); + trace_output (OP_REG_REG); } /* subr reg1, reg2 */ @@ -561,6 +981,7 @@ OP_180 () { unsigned int op0, op1, result, z, s, cy, ov; + trace_input ("subr", OP_REG_REG, 0); /* Compute the result. */ op0 = State.regs[OP[0]]; op1 = State.regs[OP[1]]; @@ -578,14 +999,17 @@ OP_180 () State.sregs[5] &= ~(PSW_Z | PSW_S | PSW_CY | PSW_OV); State.sregs[5] |= ((z ? PSW_Z : 0) | (s ? PSW_S : 0) | (cy ? PSW_CY : 0) | (ov ? PSW_OV : 0)); + trace_output (OP_REG_REG); } /* mulh reg1, reg2 */ void OP_E0 () { + trace_input ("mulh", OP_REG_REG, 0); State.regs[OP[1]] = ((State.regs[OP[1]] & 0xffff) * (State.regs[OP[0]] & 0xffff)); + trace_output (OP_REG_REG); } /* mulh sign_extend(imm5), reg2 @@ -594,22 +1018,22 @@ OP_E0 () void OP_2E0 () { - int value = OP[0]; + int value = SEXT5 (OP[0]); - value = (value << 27) >> 27; - + trace_input ("mulh", OP_IMM_REG, 0); State.regs[OP[1]] = (State.regs[OP[1]] & 0xffff) * value; + trace_output (OP_IMM_REG); } /* mulhi imm16, reg1, reg2 */ void OP_6E0 () { - int value = OP[0]; - - value = value & 0xffff; + int value = OP[0] & 0xffff; + trace_input ("mulhi", OP_IMM_REG_REG, 0); State.regs[OP[2]] = (State.regs[OP[1]] & 0xffff) * value; + trace_output (OP_IMM_REG_REG); } /* divh reg1, reg2 */ @@ -619,9 +1043,10 @@ OP_40 () unsigned int op0, op1, result, ov, s, z; int temp; + trace_input ("divh", OP_REG_REG, 0); + /* Compute the result. */ - temp = State.regs[OP[0]] & 0xffff; - temp = (temp << 16) >> 16; + temp = SEXT16 (State.regs[OP[0]]); op0 = temp; op1 = State.regs[OP[1]]; @@ -650,6 +1075,7 @@ OP_40 () State.sregs[5] &= ~(PSW_Z | PSW_S | PSW_OV); State.sregs[5] |= ((z ? PSW_Z : 0) | (s ? PSW_S : 0) | (ov ? PSW_OV : 0)); + trace_output (OP_REG_REG); } /* cmp reg, reg */ @@ -658,6 +1084,7 @@ OP_1E0 () { unsigned int op0, op1, result, z, s, cy, ov; + trace_input ("cmp", OP_REG_REG_CMP, 0); /* Compute the result. */ op0 = State.regs[OP[0]]; op1 = State.regs[OP[1]]; @@ -674,6 +1101,7 @@ OP_1E0 () State.sregs[5] &= ~(PSW_Z | PSW_S | PSW_CY | PSW_OV); State.sregs[5] |= ((z ? PSW_Z : 0) | (s ? PSW_S : 0) | (cy ? PSW_CY : 0) | (ov ? PSW_OV : 0)); + trace_output (OP_REG_REG_CMP); } /* cmp sign_extend(imm5), reg */ @@ -684,8 +1112,8 @@ OP_260 () int temp; /* Compute the result. */ - temp = OP[0]; - temp = (temp << 27) >> 27; + trace_input ("cmp", OP_IMM_REG_CMP, 0); + temp = SEXT5 (OP[0]); op0 = temp; op1 = State.regs[OP[1]]; result = op1 - op0; @@ -701,6 +1129,7 @@ OP_260 () State.sregs[5] &= ~(PSW_Z | PSW_S | PSW_CY | PSW_OV); State.sregs[5] |= ((z ? PSW_Z : 0) | (s ? PSW_S : 0) | (cy ? PSW_CY : 0) | (ov ? PSW_OV : 0)); + trace_output (OP_IMM_REG_CMP); } /* setf cccc,reg2 */ @@ -711,6 +1140,7 @@ OP_7E0 () wanted 4 bits. */ unsigned int op0, psw, result = 0; + trace_input ("setf", OP_EX1, 0); op0 = OP[0] & 0xf; psw = State.sregs[5]; @@ -769,6 +1199,7 @@ OP_7E0 () } State.regs[OP[1]] = result; + trace_output (OP_EX1); } /* satadd reg,reg */ @@ -777,6 +1208,7 @@ OP_C0 () { unsigned int op0, op1, result, z, s, cy, ov, sat; + trace_input ("satadd", OP_REG_REG, 0); /* Compute the result. */ op0 = State.regs[OP[0]]; op1 = State.regs[OP[1]]; @@ -802,6 +1234,7 @@ OP_C0 () State.regs[OP[1]] = 0x80000000; else if (sat) State.regs[OP[1]] = 0x7fffffff; + trace_output (OP_REG_REG); } /* satadd sign_extend(imm5), reg */ @@ -812,9 +1245,10 @@ OP_220 () int temp; + trace_input ("satadd", OP_IMM_REG, 0); + /* Compute the result. */ - temp = (OP[0] & 0x1f); - temp = (temp << 27) >> 27; + temp = SEXT5 (OP[0]); op0 = temp; op1 = State.regs[OP[1]]; result = op0 + op1; @@ -839,6 +1273,7 @@ OP_220 () State.regs[OP[1]] = 0x80000000; else if (sat) State.regs[OP[1]] = 0x7fffffff; + trace_output (OP_IMM_REG); } /* satsub reg1, reg2 */ @@ -847,6 +1282,8 @@ OP_A0 () { unsigned int op0, op1, result, z, s, cy, ov, sat; + trace_input ("satsub", OP_REG_REG, 0); + /* Compute the result. */ op0 = State.regs[OP[0]]; op1 = State.regs[OP[1]]; @@ -872,6 +1309,7 @@ OP_A0 () State.regs[OP[1]] = 0x80000000; else if (sat) State.regs[OP[1]] = 0x7fffffff; + trace_output (OP_REG_REG); } /* satsubi sign_extend(imm16), reg */ @@ -881,9 +1319,10 @@ OP_660 () unsigned int op0, op1, result, z, s, cy, ov, sat; int temp; + trace_input ("satsubi", OP_IMM_REG, 0); + /* Compute the result. */ - temp = (OP[0] & 0xffff); - temp = (temp << 16) >> 16; + temp = SEXT16 (OP[0]); op0 = temp; op1 = State.regs[OP[1]]; result = op1 - op0; @@ -908,13 +1347,17 @@ OP_660 () State.regs[OP[1]] = 0x80000000; else if (sat) State.regs[OP[1]] = 0x7fffffff; + trace_output (OP_IMM_REG); } +/* satsubr reg,reg */ void OP_80 () { unsigned int op0, op1, result, z, s, cy, ov, sat; + trace_input ("satsubr", OP_REG_REG, 0); + /* Compute the result. */ op0 = State.regs[OP[0]]; op1 = State.regs[OP[1]]; @@ -940,6 +1383,7 @@ OP_80 () State.regs[OP[1]] = 0x80000000; else if (sat) State.regs[OP[1]] = 0x7fffffff; + trace_output (OP_REG_REG); } /* tst reg,reg */ @@ -948,6 +1392,8 @@ OP_160 () { unsigned int op0, op1, result, z, s; + trace_input ("tst", OP_REG_REG_CMP, 0); + /* Compute the result. */ op0 = State.regs[OP[0]]; op1 = State.regs[OP[1]]; @@ -960,23 +1406,27 @@ OP_160 () /* Store the condition codes. */ State.sregs[5] &= ~(PSW_Z | PSW_S | PSW_OV); State.sregs[5] |= ((z ? PSW_Z : 0) | (s ? PSW_S : 0)); + trace_output (OP_REG_REG_CMP); } /* mov reg, reg */ void OP_0 () { + trace_input ("mov", OP_REG_REG_MOVE, 0); State.regs[OP[1]] = State.regs[OP[0]]; + trace_output (OP_REG_REG_MOVE); } /* mov sign_extend(imm5), reg */ void OP_200 () { - int value = OP[0]; + int value = SEXT5 (OP[0]); - value = (value << 27) >> 27; + trace_input ("mov", OP_IMM_REG_MOVE, 0); State.regs[OP[1]] = value; + trace_output (OP_IMM_REG_MOVE); } /* movea sign_extend(imm16), reg, reg */ @@ -984,22 +1434,22 @@ OP_200 () void OP_620 () { - int value = OP[0]; - - value = (value << 16) >> 16; + int value = SEXT16 (OP[0]); + trace_input ("movea", OP_IMM_REG_REG, 0); State.regs[OP[2]] = State.regs[OP[1]] + value; + trace_output (OP_IMM_REG_REG); } /* movhi imm16, reg, reg */ void OP_640 () { - int value = OP[0]; - - value = (value & 0xffff) << 16; + uint32 value = (OP[0] & 0xffff) << 16; + trace_input ("movhi", OP_UIMM_REG_REG, 16); State.regs[OP[2]] = State.regs[OP[1]] + value; + trace_output (OP_UIMM_REG_REG); } /* sar zero_extend(imm5),reg1 */ @@ -1008,6 +1458,7 @@ OP_2A0 () { unsigned int op0, op1, result, z, s, cy; + trace_input ("sar", OP_IMM_REG, 0); op0 = OP[0] & 0x1f; op1 = State.regs[OP[1]]; result = (signed)op1 >> op0; @@ -1022,6 +1473,7 @@ OP_2A0 () State.sregs[5] &= ~(PSW_Z | PSW_S | PSW_OV | PSW_CY); State.sregs[5] |= ((z ? PSW_Z : 0) | (s ? PSW_S : 0) | (cy ? PSW_CY : 0)); + trace_output (OP_IMM_REG); } /* sar reg1, reg2 */ @@ -1030,6 +1482,7 @@ OP_A007E0 () { unsigned int op0, op1, result, z, s, cy; + trace_input ("sar", OP_REG_REG, 0); op0 = State.regs[OP[0]] & 0x1f; op1 = State.regs[OP[1]]; result = (signed)op1 >> op0; @@ -1044,6 +1497,7 @@ OP_A007E0 () State.sregs[5] &= ~(PSW_Z | PSW_S | PSW_OV | PSW_CY); State.sregs[5] |= ((z ? PSW_Z : 0) | (s ? PSW_S : 0) | (cy ? PSW_CY : 0)); + trace_output (OP_REG_REG); } /* shl zero_extend(imm5),reg1 */ @@ -1052,6 +1506,7 @@ OP_2C0 () { unsigned int op0, op1, result, z, s, cy; + trace_input ("shl", OP_IMM_REG, 0); op0 = OP[0] & 0x1f; op1 = State.regs[OP[1]]; result = op1 << op0; @@ -1066,6 +1521,7 @@ OP_2C0 () State.sregs[5] &= ~(PSW_Z | PSW_S | PSW_OV | PSW_CY); State.sregs[5] |= ((z ? PSW_Z : 0) | (s ? PSW_S : 0) | (cy ? PSW_CY : 0)); + trace_output (OP_IMM_REG); } /* shl reg1, reg2 */ @@ -1074,6 +1530,7 @@ OP_C007E0 () { unsigned int op0, op1, result, z, s, cy; + trace_input ("shl", OP_REG_REG, 0); op0 = State.regs[OP[0]] & 0x1f; op1 = State.regs[OP[1]]; result = op1 << op0; @@ -1088,6 +1545,7 @@ OP_C007E0 () State.sregs[5] &= ~(PSW_Z | PSW_S | PSW_OV | PSW_CY); State.sregs[5] |= ((z ? PSW_Z : 0) | (s ? PSW_S : 0) | (cy ? PSW_CY : 0)); + trace_output (OP_REG_REG); } /* shr zero_extend(imm5),reg1 */ @@ -1096,6 +1554,7 @@ OP_280 () { unsigned int op0, op1, result, z, s, cy; + trace_input ("shr", OP_IMM_REG, 0); op0 = OP[0] & 0x1f; op1 = State.regs[OP[1]]; result = op1 >> op0; @@ -1110,6 +1569,7 @@ OP_280 () State.sregs[5] &= ~(PSW_Z | PSW_S | PSW_OV | PSW_CY); State.sregs[5] |= ((z ? PSW_Z : 0) | (s ? PSW_S : 0) | (cy ? PSW_CY : 0)); + trace_output (OP_IMM_REG); } /* shr reg1, reg2 */ @@ -1118,6 +1578,7 @@ OP_8007E0 () { unsigned int op0, op1, result, z, s, cy; + trace_input ("shr", OP_REG_REG, 0); op0 = State.regs[OP[0]] & 0x1f; op1 = State.regs[OP[1]]; result = op1 >> op0; @@ -1132,6 +1593,7 @@ OP_8007E0 () State.sregs[5] &= ~(PSW_Z | PSW_S | PSW_OV | PSW_CY); State.sregs[5] |= ((z ? PSW_Z : 0) | (s ? PSW_S : 0) | (cy ? PSW_CY : 0)); + trace_output (OP_REG_REG); } /* or reg, reg */ @@ -1140,6 +1602,8 @@ OP_100 () { unsigned int op0, op1, result, z, s; + trace_input ("or", OP_REG_REG, 0); + /* Compute the result. */ op0 = State.regs[OP[0]]; op1 = State.regs[OP[1]]; @@ -1153,6 +1617,7 @@ OP_100 () State.regs[OP[1]] = result; State.sregs[5] &= ~(PSW_Z | PSW_S | PSW_OV); State.sregs[5] |= ((z ? PSW_Z : 0) | (s ? PSW_S : 0)); + trace_output (OP_REG_REG); } /* ori zero_extend(imm16), reg, reg */ @@ -1161,6 +1626,7 @@ OP_680 () { unsigned int op0, op1, result, z, s; + trace_input ("ori", OP_UIMM_REG_REG, 0); op0 = OP[0] & 0xffff; op1 = State.regs[OP[1]]; result = op0 | op1; @@ -1173,6 +1639,7 @@ OP_680 () State.regs[OP[2]] = result; State.sregs[5] &= ~(PSW_Z | PSW_S | PSW_OV); State.sregs[5] |= ((z ? PSW_Z : 0) | (s ? PSW_S : 0)); + trace_output (OP_UIMM_REG_REG); } /* and reg, reg */ @@ -1181,6 +1648,8 @@ OP_140 () { unsigned int op0, op1, result, z, s; + trace_input ("and", OP_REG_REG, 0); + /* Compute the result. */ op0 = State.regs[OP[0]]; op1 = State.regs[OP[1]]; @@ -1194,6 +1663,7 @@ OP_140 () State.regs[OP[1]] = result; State.sregs[5] &= ~(PSW_Z | PSW_S | PSW_OV); State.sregs[5] |= ((z ? PSW_Z : 0) | (s ? PSW_S : 0)); + trace_output (OP_REG_REG); } /* andi zero_extend(imm16), reg, reg */ @@ -1202,6 +1672,7 @@ OP_6C0 () { unsigned int op0, op1, result, z; + trace_input ("andi", OP_UIMM_REG_REG, 0); op0 = OP[0] & 0xffff; op1 = State.regs[OP[1]]; result = op0 & op1; @@ -1213,6 +1684,7 @@ OP_6C0 () State.regs[OP[2]] = result; State.sregs[5] &= ~(PSW_Z | PSW_S | PSW_OV); State.sregs[5] |= (z ? PSW_Z : 0); + trace_output (OP_UIMM_REG_REG); } /* xor reg, reg */ @@ -1221,6 +1693,8 @@ OP_120 () { unsigned int op0, op1, result, z, s; + trace_input ("xor", OP_REG_REG, 0); + /* Compute the result. */ op0 = State.regs[OP[0]]; op1 = State.regs[OP[1]]; @@ -1234,6 +1708,7 @@ OP_120 () State.regs[OP[1]] = result; State.sregs[5] &= ~(PSW_Z | PSW_S | PSW_OV); State.sregs[5] |= ((z ? PSW_Z : 0) | (s ? PSW_S : 0)); + trace_output (OP_REG_REG); } /* xori zero_extend(imm16), reg, reg */ @@ -1242,6 +1717,7 @@ OP_6A0 () { unsigned int op0, op1, result, z, s; + trace_input ("xori", OP_UIMM_REG_REG, 0); op0 = OP[0] & 0xffff; op1 = State.regs[OP[1]]; result = op0 ^ op1; @@ -1254,6 +1730,7 @@ OP_6A0 () State.regs[OP[2]] = result; State.sregs[5] &= ~(PSW_Z | PSW_S | PSW_OV); State.sregs[5] |= ((z ? PSW_Z : 0) | (s ? PSW_S : 0)); + trace_output (OP_UIMM_REG_REG); } /* not reg1, reg2 */ @@ -1262,6 +1739,7 @@ OP_20 () { unsigned int op0, result, z, s; + trace_input ("not", OP_REG_REG_MOVE, 0); /* Compute the result. */ op0 = State.regs[OP[0]]; result = ~op0; @@ -1274,6 +1752,7 @@ OP_20 () State.regs[OP[1]] = result; State.sregs[5] &= ~(PSW_Z | PSW_S | PSW_OV); State.sregs[5] |= ((z ? PSW_Z : 0) | (s ? PSW_S : 0)); + trace_output (OP_REG_REG_MOVE); } /* set1 */ @@ -1283,10 +1762,10 @@ OP_7C0 () unsigned int op0, op1, op2; int temp; + trace_input ("set1", OP_BIT, 0); op0 = State.regs[OP[0]]; op1 = OP[1] & 0x7; - temp = OP[2]; - temp = (temp << 16) >> 16; + temp = SEXT16 (OP[2]); op2 = temp; temp = get_byte (State.mem + op0 + op2); State.sregs[5] &= ~PSW_Z; @@ -1294,6 +1773,7 @@ OP_7C0 () State.sregs[5] |= PSW_Z; temp |= (1 << op1); put_byte (State.mem + op0 + op2, temp); + trace_output (OP_BIT); } /* not1 */ @@ -1303,10 +1783,10 @@ OP_47C0 () unsigned int op0, op1, op2; int temp; + trace_input ("not1", OP_BIT, 0); op0 = State.regs[OP[0]]; op1 = OP[1] & 0x7; - temp = OP[2]; - temp = (temp << 16) >> 16; + temp = SEXT16 (OP[2]); op2 = temp; temp = get_byte (State.mem + op0 + op2); State.sregs[5] &= ~PSW_Z; @@ -1314,6 +1794,7 @@ OP_47C0 () State.sregs[5] |= PSW_Z; temp ^= (1 << op1); put_byte (State.mem + op0 + op2, temp); + trace_output (OP_BIT); } /* clr1 */ @@ -1323,10 +1804,10 @@ OP_87C0 () unsigned int op0, op1, op2; int temp; + trace_input ("clr1", OP_BIT, 0); op0 = State.regs[OP[0]]; op1 = OP[1] & 0x7; - temp = OP[2]; - temp = (temp << 16) >> 16; + temp = SEXT16 (OP[2]); op2 = temp; temp = get_byte (State.mem + op0 + op2); State.sregs[5] &= ~PSW_Z; @@ -1334,6 +1815,7 @@ OP_87C0 () State.sregs[5] |= PSW_Z; temp &= ~(1 << op1); put_byte (State.mem + op0 + op2, temp); + trace_output (OP_BIT); } /* tst1 */ @@ -1343,42 +1825,51 @@ OP_C7C0 () unsigned int op0, op1, op2; int temp; + trace_input ("tst1", OP_BIT, 0); op0 = State.regs[OP[0]]; op1 = OP[1] & 0x7; - temp = OP[2]; - temp = (temp << 16) >> 16; + temp = SEXT16 (OP[2]); op2 = temp; temp = get_byte (State.mem + op0 + op2); State.sregs[5] &= ~PSW_Z; if ((temp & (1 << op1)) == 0) State.sregs[5] |= PSW_Z; + trace_output (OP_BIT); } /* di */ void OP_16007E0 () { + trace_input ("di", OP_NONE, 0); State.sregs[5] |= PSW_ID; + trace_output (OP_NONE); } /* ei */ void OP_16087E0 () { + trace_input ("ei", OP_NONE, 0); State.sregs[5] &= ~PSW_ID; + trace_output (OP_NONE); } /* halt, not supported */ void OP_12007E0 () { + trace_input ("halt", OP_NONE, 0); State.exception = SIGQUIT; + trace_output (OP_NONE); } /* reti, not supported */ void OP_14007E0 () { + trace_input ("reti", OP_NONE, 0); + trace_output (OP_NONE); abort (); } @@ -1388,6 +1879,9 @@ OP_10007E0 () { extern int errno; + trace_input ("trap", OP_TRAP, 0); + trace_output (OP_TRAP); + /* Trap 0 is used for simulating low-level I/O */ if (OP[0] == 0) @@ -1539,8 +2033,10 @@ OP_2007E0 () { unsigned int op0; + trace_input ("ldsr", OP_LDSR, 0); op0 = State.regs[OP[0]]; State.sregs[OP[1]] = op0; + trace_output (OP_LDSR); } /* stsr, not supported */ @@ -1549,7 +2045,8 @@ OP_4007E0 () { unsigned int op0; + trace_input ("stsr", OP_STSR, 0); op0 = State.sregs[OP[1]]; State.regs[OP[0]] = op0; + trace_output (OP_STSR); } - -- 2.30.2