From eae03bbc9d865e42cfdaa7ba63efa832ed233205 Mon Sep 17 00:00:00 2001 From: Gabe Black Date: Mon, 3 Feb 2020 17:08:18 -0800 Subject: [PATCH] arch,cpu: Make the CPU's ISA parameter type BaseISA. This is mostly only a superficial change since the isa parameter is then dynamic cast to the ISA specific version inside the various consumers, currently the SimpleThread, O3CPU and Decoder classes. If those aren't being used, for instance in the fast model CPUs, then you can use a different ISA implementation without any type clashes. Change-Id: I2226ef60f9a471ae51b8bfce8683033f7854197a Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/25009 Reviewed-by: Gabe Black Maintainer: Gabe Black Tested-by: kokoro --- src/cpu/BaseCPU.py | 9 +-------- src/cpu/o3/cpu.cc | 12 ++++++++---- src/cpu/o3/fetch_impl.hh | 3 ++- src/cpu/simple_thread.cc | 17 +++++++++++------ src/cpu/simple_thread.hh | 4 ++-- 5 files changed, 24 insertions(+), 21 deletions(-) diff --git a/src/cpu/BaseCPU.py b/src/cpu/BaseCPU.py index 57f0f2f3d..09a8b331f 100644 --- a/src/cpu/BaseCPU.py +++ b/src/cpu/BaseCPU.py @@ -66,37 +66,30 @@ if buildEnv['TARGET_ISA'] == 'alpha': from m5.objects.AlphaTLB import AlphaDTB as ArchDTB, AlphaITB as ArchITB from m5.objects.AlphaInterrupts import AlphaInterrupts as ArchInterrupts from m5.objects.AlphaISA import AlphaISA as ArchISA - ArchISAsParam = VectorParam.AlphaISA elif buildEnv['TARGET_ISA'] == 'sparc': from m5.objects.SparcTLB import SparcTLB as ArchDTB, SparcTLB as ArchITB from m5.objects.SparcInterrupts import SparcInterrupts as ArchInterrupts from m5.objects.SparcISA import SparcISA as ArchISA - ArchISAsParam = VectorParam.SparcISA elif buildEnv['TARGET_ISA'] == 'x86': from m5.objects.X86TLB import X86TLB as ArchDTB, X86TLB as ArchITB from m5.objects.X86LocalApic import X86LocalApic as ArchInterrupts from m5.objects.X86ISA import X86ISA as ArchISA - ArchISAsParam = VectorParam.X86ISA elif buildEnv['TARGET_ISA'] == 'mips': from m5.objects.MipsTLB import MipsTLB as ArchDTB, MipsTLB as ArchITB from m5.objects.MipsInterrupts import MipsInterrupts as ArchInterrupts from m5.objects.MipsISA import MipsISA as ArchISA - ArchISAsParam = VectorParam.MipsISA elif buildEnv['TARGET_ISA'] == 'arm': from m5.objects.ArmTLB import ArmDTB as ArchDTB, ArmITB as ArchITB from m5.objects.ArmInterrupts import ArmInterrupts as ArchInterrupts from m5.objects.ArmISA import ArmISA as ArchISA - ArchISAsParam = VectorParam.ArmISA elif buildEnv['TARGET_ISA'] == 'power': from m5.objects.PowerTLB import PowerTLB as ArchDTB, PowerTLB as ArchITB from m5.objects.PowerInterrupts import PowerInterrupts as ArchInterrupts from m5.objects.PowerISA import PowerISA as ArchISA - ArchISAsParam = VectorParam.PowerISA elif buildEnv['TARGET_ISA'] == 'riscv': from m5.objects.RiscvTLB import RiscvTLB as ArchDTB, RiscvTLB as ArchITB from m5.objects.RiscvInterrupts import RiscvInterrupts as ArchInterrupts from m5.objects.RiscvISA import RiscvISA as ArchISA - ArchISAsParam = VectorParam.RiscvISA else: print("Don't know what object types to use for ISA %s" % buildEnv['TARGET_ISA']) @@ -176,7 +169,7 @@ class BaseCPU(ClockedObject): if buildEnv['TARGET_ISA'] == 'power': UnifiedTLB = Param.Bool(True, "Is this a Unified TLB?") interrupts = VectorParam.BaseInterrupts([], "Interrupt Controller") - isa = ArchISAsParam([], "ISA instance") + isa = VectorParam.BaseISA([], "ISA instance") max_insts_all_threads = Param.Counter(0, "terminate when all threads have reached this inst count") diff --git a/src/cpu/o3/cpu.cc b/src/cpu/o3/cpu.cc index e4f1c0464..27800dea5 100644 --- a/src/cpu/o3/cpu.cc +++ b/src/cpu/o3/cpu.cc @@ -109,9 +109,6 @@ FullO3CPU::FullO3CPU(DerivO3CPUParams *params) iew(this, params), commit(this, params), - /* It is mandatory that all SMT threads use the same renaming mode as - * they are sharing registers and rename */ - vecMode(RenameMode::init(params->isa[0])), regFile(params->numPhysIntRegs, params->numPhysFloatRegs, params->numPhysVecRegs, @@ -141,6 +138,12 @@ FullO3CPU::FullO3CPU(DerivO3CPUParams *params) system(params->system), lastRunningCycle(curCycle()) { + auto *the_isa = dynamic_cast(params->isa[0]); + assert(the_isa); + /* It is mandatory that all SMT threads use the same renaming mode as + * they are sharing registers and rename */ + vecMode = RenameMode::init(the_isa); + if (!params->switched_out) { _status = Running; } else { @@ -220,7 +223,8 @@ FullO3CPU::FullO3CPU(DerivO3CPUParams *params) // Setup the rename map for whichever stages need it. for (ThreadID tid = 0; tid < numThreads; tid++) { - isa[tid] = params->isa[tid]; + isa[tid] = dynamic_cast(params->isa[tid]); + assert(isa[tid]); assert(RenameMode::equalsInit(isa[tid], isa[0])); // Only Alpha has an FP zero register, so for other ISAs we diff --git a/src/cpu/o3/fetch_impl.hh b/src/cpu/o3/fetch_impl.hh index 47b1ad0c5..c8a8a1fa9 100644 --- a/src/cpu/o3/fetch_impl.hh +++ b/src/cpu/o3/fetch_impl.hh @@ -142,7 +142,8 @@ DefaultFetch::DefaultFetch(O3CPU *_cpu, DerivO3CPUParams *params) branchPred = params->branchPred; for (ThreadID tid = 0; tid < numThreads; tid++) { - decoder[tid] = new TheISA::Decoder(params->isa[tid]); + decoder[tid] = new TheISA::Decoder( + dynamic_cast(params->isa[tid])); // Create space to buffer the cache line data, // which may not hold the entire cache line. fetchBuffer[tid] = new uint8_t[fetchBufferSize]; diff --git a/src/cpu/simple_thread.cc b/src/cpu/simple_thread.cc index 79333cb1b..c4785cfa3 100644 --- a/src/cpu/simple_thread.cc +++ b/src/cpu/simple_thread.cc @@ -75,24 +75,29 @@ using namespace std; // constructor SimpleThread::SimpleThread(BaseCPU *_cpu, int _thread_num, System *_sys, Process *_process, BaseTLB *_itb, - BaseTLB *_dtb, TheISA::ISA *_isa) - : ThreadState(_cpu, _thread_num, _process), isa(_isa), + BaseTLB *_dtb, BaseISA *_isa) + : ThreadState(_cpu, _thread_num, _process), + isa(dynamic_cast(_isa)), predicate(true), memAccPredicate(true), comInstEventQueue("instruction-based event queue"), - system(_sys), itb(_itb), dtb(_dtb), decoder(TheISA::Decoder(_isa)) + system(_sys), itb(_itb), dtb(_dtb), decoder(TheISA::Decoder(isa)) { + assert(isa); clearArchRegs(); quiesceEvent = new EndQuiesceEvent(this); } SimpleThread::SimpleThread(BaseCPU *_cpu, int _thread_num, System *_sys, BaseTLB *_itb, BaseTLB *_dtb, - TheISA::ISA *_isa, bool use_kernel_stats) - : ThreadState(_cpu, _thread_num, NULL), isa(_isa), + BaseISA *_isa, bool use_kernel_stats) + : ThreadState(_cpu, _thread_num, NULL), + isa(dynamic_cast(_isa)), predicate(true), memAccPredicate(true), comInstEventQueue("instruction-based event queue"), - system(_sys), itb(_itb), dtb(_dtb), decoder(TheISA::Decoder(_isa)) + system(_sys), itb(_itb), dtb(_dtb), decoder(TheISA::Decoder(isa)) { + assert(isa); + quiesceEvent = new EndQuiesceEvent(this); clearArchRegs(); diff --git a/src/cpu/simple_thread.hh b/src/cpu/simple_thread.hh index fabcbb83b..7f799d80b 100644 --- a/src/cpu/simple_thread.hh +++ b/src/cpu/simple_thread.hh @@ -144,12 +144,12 @@ class SimpleThread : public ThreadState, public ThreadContext // constructor: initialize SimpleThread from given process structure // FS SimpleThread(BaseCPU *_cpu, int _thread_num, System *_system, - BaseTLB *_itb, BaseTLB *_dtb, TheISA::ISA *_isa, + BaseTLB *_itb, BaseTLB *_dtb, BaseISA *_isa, bool use_kernel_stats = true); // SE SimpleThread(BaseCPU *_cpu, int _thread_num, System *_system, Process *_process, BaseTLB *_itb, BaseTLB *_dtb, - TheISA::ISA *_isa); + BaseISA *_isa); virtual ~SimpleThread() {} -- 2.30.2