From eae43e2db430c951018b5cb70f047de84ad010b0 Mon Sep 17 00:00:00 2001
From: Clifford Wolf <clifford@clifford.at>
Date: Thu, 24 Oct 2013 10:59:27 +0200
Subject: [PATCH] Fixed handling of boolean attributes (kernel)

---
 backends/verilog/verilog_backend.cc |  8 ++++----
 frontends/verilog/parser.y          |  2 +-
 kernel/rtlil.h                      | 22 +++++++++++++++++-----
 3 files changed, 22 insertions(+), 10 deletions(-)

diff --git a/backends/verilog/verilog_backend.cc b/backends/verilog/verilog_backend.cc
index d64deb640..0eee4af40 100644
--- a/backends/verilog/verilog_backend.cc
+++ b/backends/verilog/verilog_backend.cc
@@ -167,6 +167,8 @@ void dump_const(FILE *f, RTLIL::Const &data, int width = -1, int offset = 0, boo
 		} else {
 	dump_bits:
 			fprintf(f, "%d'b", width);
+			if (width == 0)
+				fprintf(f, "0");
 			for (int i = offset+width-1; i >= offset; i--) {
 				assert(i < (int)data.bits.size());
 				switch (data.bits[i]) {
@@ -234,10 +236,8 @@ void dump_attributes(FILE *f, std::string indent, std::map<RTLIL::IdString, RTLI
 		return;
 	for (auto it = attributes.begin(); it != attributes.end(); it++) {
 		fprintf(f, "%s" "%s %s", indent.c_str(), attr2comment ? "/*" : "(*", id(it->first).c_str());
-		if (it->second.bits.size() > 0) {
-			fprintf(f, " = ");
-			dump_const(f, it->second);
-		}
+		fprintf(f, " = ");
+		dump_const(f, it->second);
 		fprintf(f, " %s%c", attr2comment ? "*/" : "*)", term);
 	}
 }
diff --git a/frontends/verilog/parser.y b/frontends/verilog/parser.y
index ba0efcf51..59d0a5700 100644
--- a/frontends/verilog/parser.y
+++ b/frontends/verilog/parser.y
@@ -179,7 +179,7 @@ attr_assign:
 	hierarchical_id {
 		if (attr_list.count(*$1) != 0)
 			delete attr_list[*$1];
-		attr_list[*$1] = AstNode::mkconst_int(0, false, 0);
+		attr_list[*$1] = AstNode::mkconst_int(1, false);
 		delete $1;
 	} |
 	hierarchical_id '=' expr {
diff --git a/kernel/rtlil.h b/kernel/rtlil.h
index b69dc8143..87271bbf9 100644
--- a/kernel/rtlil.h
+++ b/kernel/rtlil.h
@@ -233,6 +233,17 @@ struct RTLIL::Design {
 	}
 };
 
+#define RTLIL_ATTRIBUTE_MEMBERS                                \
+	std::map<RTLIL::IdString, RTLIL::Const> attributes;    \
+	void set_bool_attribute(RTLIL::IdString id) {          \
+		attributes[id] = RTLIL::Const(1);              \
+	}                                                      \
+	bool get_bool_attribute(RTLIL::IdString id) const {    \
+		if (attributes.count(id) == 0)                 \
+			return false;                          \
+		return attributes.at(id).as_bool();            \
+	}
+
 struct RTLIL::Module {
 	RTLIL::IdString name;
 	std::map<RTLIL::IdString, RTLIL::Wire*> wires;
@@ -240,7 +251,7 @@ struct RTLIL::Module {
 	std::map<RTLIL::IdString, RTLIL::Cell*> cells;
 	std::map<RTLIL::IdString, RTLIL::Process*> processes;
 	std::vector<RTLIL::SigSig> connections;
-	std::map<RTLIL::IdString, RTLIL::Const> attributes;
+	RTLIL_ATTRIBUTE_MEMBERS
 	virtual ~Module();
 	virtual RTLIL::IdString derive(RTLIL::Design *design, std::map<RTLIL::IdString, RTLIL::Const> parameters);
 	virtual void update_auto_wires(std::map<RTLIL::IdString, int> auto_sizes);
@@ -255,20 +266,21 @@ struct RTLIL::Module {
 	template<typename T> void rewrite_sigspecs(T functor);
 	void cloneInto(RTLIL::Module *new_mod) const;
 	virtual RTLIL::Module *clone() const;
+
 };
 
 struct RTLIL::Wire {
 	RTLIL::IdString name;
 	int width, start_offset, port_id;
 	bool port_input, port_output, auto_width;
-	std::map<RTLIL::IdString, RTLIL::Const> attributes;
+	RTLIL_ATTRIBUTE_MEMBERS
 	Wire();
 };
 
 struct RTLIL::Memory {
 	RTLIL::IdString name;
 	int width, start_offset, size;
-	std::map<RTLIL::IdString, RTLIL::Const> attributes;
+	RTLIL_ATTRIBUTE_MEMBERS
 	Memory();
 };
 
@@ -276,8 +288,8 @@ struct RTLIL::Cell {
 	RTLIL::IdString name;
 	RTLIL::IdString type;
 	std::map<RTLIL::IdString, RTLIL::SigSpec> connections;
-	std::map<RTLIL::IdString, RTLIL::Const> attributes;
 	std::map<RTLIL::IdString, RTLIL::Const> parameters;
+	RTLIL_ATTRIBUTE_MEMBERS
 	void optimize();
 
 	template<typename T> void rewrite_sigspecs(T functor);
@@ -377,7 +389,7 @@ struct RTLIL::SyncRule {
 
 struct RTLIL::Process {
 	RTLIL::IdString name;
-	std::map<RTLIL::IdString, RTLIL::Const> attributes;
+	RTLIL_ATTRIBUTE_MEMBERS
 	RTLIL::CaseRule root_case;
 	std::vector<RTLIL::SyncRule*> syncs;
 	~Process();
-- 
2.30.2