From eaef2e7d95202e8ce3ee06178299e57a1c2a3b37 Mon Sep 17 00:00:00 2001
From: whitequark <cz@m-labs.hk>
Date: Tue, 1 Jan 2019 03:08:10 +0000
Subject: [PATCH] hdl.mem: add DummyPort, for testing and verification.

---
 nmigen/hdl/mem.py           | 28 +++++++++++++++++++++++++++-
 nmigen/test/test_hdl_mem.py | 18 ++++++++++++++++++
 2 files changed, 45 insertions(+), 1 deletion(-)

diff --git a/nmigen/hdl/mem.py b/nmigen/hdl/mem.py
index 4863fd8..deffc46 100644
--- a/nmigen/hdl/mem.py
+++ b/nmigen/hdl/mem.py
@@ -3,7 +3,7 @@ from .ast import *
 from .ir import Instance
 
 
-__all__ = ["Memory"]
+__all__ = ["Memory", "ReadPort", "WritePort", "DummyPort"]
 
 
 class Memory:
@@ -179,3 +179,29 @@ class WritePort:
         for signal in self.memory._array:
             f.add_driver(signal, self.domain)
         return f
+
+
+class DummyPort:
+    """Dummy memory port.
+
+    This port can be used in place of either a read or a write port for testing and verification.
+    It does not include any read/write port specific attributes, i.e. none besides ``"domain"``;
+    any such attributes may be set manually.
+    """
+    def __init__(self, width, addr_bits, domain="sync", name=None, granularity=None):
+        self.domain = domain
+
+        if granularity is None:
+            granularity = width
+        if name is None:
+            try:
+                name = tracer.get_var_name(depth=2)
+            except tracer.NameNotFound:
+                name = "dummy"
+
+        self.addr = Signal(addr_bits,
+                           name="{}_addr".format(name))
+        self.data = Signal(width,
+                           name="{}_data".format(name))
+        self.en   = Signal(width // granularity,
+                           name="{}_en".format(name))
diff --git a/nmigen/test/test_hdl_mem.py b/nmigen/test/test_hdl_mem.py
index 22ad5e3..0b37d48 100644
--- a/nmigen/test/test_hdl_mem.py
+++ b/nmigen/test/test_hdl_mem.py
@@ -107,3 +107,21 @@ class MemoryTestCase(FHDLTestCase):
         with self.assertRaises(ValueError,
                 msg="Write port granularity must divide memory width evenly"):
             mem.write_port(granularity=3)
+
+
+class DummyPortTestCase(FHDLTestCase):
+    def test_name(self):
+        p1 = DummyPort(width=8, addr_bits=2)
+        self.assertEqual(p1.addr.name, "p1_addr")
+        p2 = [DummyPort(width=8, addr_bits=2)][0]
+        self.assertEqual(p2.addr.name, "dummy_addr")
+        p3 = DummyPort(width=8, addr_bits=2, name="foo")
+        self.assertEqual(p3.addr.name, "foo_addr")
+
+    def test_sizes(self):
+        p1 = DummyPort(width=8, addr_bits=2)
+        self.assertEqual(p1.addr.nbits, 2)
+        self.assertEqual(p1.data.nbits, 8)
+        self.assertEqual(p1.en.nbits, 1)
+        p2 = DummyPort(width=8, addr_bits=2, granularity=2)
+        self.assertEqual(p2.en.nbits, 4)
-- 
2.30.2