From eaf9228c48c2939e0dbf9aebc197416973025423 Mon Sep 17 00:00:00 2001 From: Luke Kenneth Casson Leighton Date: Tue, 13 Apr 2021 18:52:42 +0000 Subject: [PATCH] use METAL10 for topRoutingLayer --- experiments10_verilog/freepdk_c4m45/doDesign.py | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/experiments10_verilog/freepdk_c4m45/doDesign.py b/experiments10_verilog/freepdk_c4m45/doDesign.py index 2628842..613e7e3 100644 --- a/experiments10_verilog/freepdk_c4m45/doDesign.py +++ b/experiments10_verilog/freepdk_c4m45/doDesign.py @@ -77,7 +77,7 @@ def scriptMain ( **kw ): adderConf.cfg.anabatic.searchHalo = 2 adderConf.cfg.anabatic.globalIterations = 20 adderConf.cfg.anabatic.routingGauge = 'FlexLib' - adderConf.cfg.anabatic.topRoutingLayer = 'METAL5' + adderConf.cfg.anabatic.topRoutingLayer = 'METAL10' adderConf.cfg.block.spareSide = u(7*13) #adderConf.cfg.chip.padCoreSide = 'North' adderConf.cfg.chip.supplyRailWidth = u(35) -- 2.30.2