From eb0107e7c9767381c8235e0ae327d228787b223a Mon Sep 17 00:00:00 2001
From: lkcl <lkcl@web>
Date: Wed, 19 Jun 2019 20:20:27 +0100
Subject: [PATCH]

---
 simple_v_extension/specification.mdwn | 3 ++-
 1 file changed, 2 insertions(+), 1 deletion(-)

diff --git a/simple_v_extension/specification.mdwn b/simple_v_extension/specification.mdwn
index 3a705a90f..ccf4d55fe 100644
--- a/simple_v_extension/specification.mdwn
+++ b/simple_v_extension/specification.mdwn
@@ -2290,7 +2290,8 @@ and VL need to be set.
 By contrast, the VLIW prefix is only 16 bits, the VL/MAX/SubVL block is
 only 16 bits, and as long as not too many predicates and register vector
 qualifiers are specified, several 32-bit and 16-bit opcodes can fit into the
-format.
+format. If the full flexibility of the 16 bit block formats are not needed, more space is saved by using the 8 bit formats.
+
 In this light, embedding the VL/MAXVL, PredCam and RegCam CSR entries into
 a VLIW format makes a lot of sense.
 
-- 
2.30.2