From eb0c1339c3339f51744e01e548a3091ff9c056fa Mon Sep 17 00:00:00 2001 From: Luke Kenneth Casson Leighton Date: Mon, 1 Oct 2018 12:00:27 +0100 Subject: [PATCH] whoops vloop continuation logic the wrong way round the loop has to continue if there is one vectorised register left rather than stop if there is *no* vectorised registers --- riscv/insn_template_sv.cc | 4 ++-- riscv/sv.cc | 4 ++-- riscv/sv_decode.h | 8 ++++---- 3 files changed, 8 insertions(+), 8 deletions(-) diff --git a/riscv/insn_template_sv.cc b/riscv/insn_template_sv.cc index 92404e5..5da73bb 100644 --- a/riscv/insn_template_sv.cc +++ b/riscv/insn_template_sv.cc @@ -53,9 +53,9 @@ reg_t FN(processor_t* p, insn_t s_insn, reg_t pc) #endif if (vlen > 1) { - fprintf(stderr, "reg %s %x vloop %d vlen %d stop %d pred %lx\n", + fprintf(stderr, "reg %s %x vloop %d vlen %d stop %d pred %lx rd%lx\n", xstr(INSN), INSNCODE, voffs, vlen, insn.stop_vloop(), - dest_pred & (1<active) { - vloop_continue = false; return reg; // not active: return as-is } + vloop_continue = true; // next we go through the lookup table. *THIS* is why the // sv_reg_entry table is 32 entries (5-bit) *NOT* 6 bits @@ -92,9 +92,9 @@ uint64_t sv_insn_t::remap(uint64_t reg, bool intreg, int &voffs, int &newoffs) // we return the re-mapped register... if (!r->isvec) // scalar { - vloop_continue = false; return reg; } + vloop_continue = true; // aaand now, as it's a "vector", FINALLY we can add on the loop-offset // which was passed in to the sv_insn_t constructor (by reference) diff --git a/riscv/sv_decode.h b/riscv/sv_decode.h index 3999d06..5d2b2fc 100644 --- a/riscv/sv_decode.h +++ b/riscv/sv_decode.h @@ -22,7 +22,7 @@ class sv_insn_t: public insn_t public: sv_insn_t(processor_t *pr, insn_bits_t bits, unsigned int f, uint64_t &p_rd, uint64_t &p_rs1, uint64_t &p_rs2, uint64_t &p_rs3) : - insn_t(bits), p(pr), vloop_continue(true), fimap(f), + insn_t(bits), p(pr), vloop_continue(false), fimap(f), cached_rd(0xff), cached_rs1(0xff), cached_rs2(0xff), cached_rs3(0xff), offs_rd(0), offs_rs1(0), @@ -73,7 +73,7 @@ public: sv_pred_entry* get_predentry(uint64_t reg, bool isint); reg_t predicate(uint64_t reg, bool isint, bool &zeroing); - void reset_vloop_check(void) { vloop_continue = true; } + void reset_vloop_check(void) { vloop_continue = false; } bool stop_vloop(void) { return !vloop_continue; } private: @@ -113,9 +113,9 @@ private: } else { - if (!sv_check_reg(isint, reg)) + if (sv_check_reg(isint, reg)) { - vloop_continue = false; + vloop_continue = true; } } return cached; -- 2.30.2