From eb22f5bf6f66ada75a9b6cc0e383cce79773490e Mon Sep 17 00:00:00 2001 From: =?utf8?q?Marek=20Ol=C5=A1=C3=A1k?= Date: Sat, 15 Oct 2016 14:38:59 +0200 Subject: [PATCH] radeonsi/gfx9: SPI_SHADER_USER_DATA changes MIME-Version: 1.0 Content-Type: text/plain; charset=utf8 Content-Transfer-Encoding: 8bit Reviewed-by: Nicolai Hähnle --- src/gallium/drivers/radeonsi/si_descriptors.c | 45 ++++++++++++++----- 1 file changed, 34 insertions(+), 11 deletions(-) diff --git a/src/gallium/drivers/radeonsi/si_descriptors.c b/src/gallium/drivers/radeonsi/si_descriptors.c index fb82f8f3ee9..5450dbe0dd8 100644 --- a/src/gallium/drivers/radeonsi/si_descriptors.c +++ b/src/gallium/drivers/radeonsi/si_descriptors.c @@ -1835,15 +1835,21 @@ static void si_set_user_data_base(struct si_context *sctx, void si_shader_change_notify(struct si_context *sctx) { /* VS can be bound as VS, ES, or LS. */ - if (sctx->tes_shader.cso) - si_set_user_data_base(sctx, PIPE_SHADER_VERTEX, - R_00B530_SPI_SHADER_USER_DATA_LS_0); - else if (sctx->gs_shader.cso) + if (sctx->tes_shader.cso) { + if (sctx->b.chip_class >= GFX9) { + si_set_user_data_base(sctx, PIPE_SHADER_VERTEX, + R_00B430_SPI_SHADER_USER_DATA_LS_0); + } else { + si_set_user_data_base(sctx, PIPE_SHADER_VERTEX, + R_00B530_SPI_SHADER_USER_DATA_LS_0); + } + } else if (sctx->gs_shader.cso) { si_set_user_data_base(sctx, PIPE_SHADER_VERTEX, R_00B330_SPI_SHADER_USER_DATA_ES_0); - else + } else { si_set_user_data_base(sctx, PIPE_SHADER_VERTEX, R_00B130_SPI_SHADER_USER_DATA_VS_0); + } /* TES can be bound as ES, VS, or not bound. */ if (sctx->tes_shader.cso) { @@ -1890,12 +1896,19 @@ void si_emit_graphics_shader_userdata(struct si_context *sctx, R_00B030_SPI_SHADER_USER_DATA_PS_0); si_emit_shader_pointer(sctx, descs, R_00B130_SPI_SHADER_USER_DATA_VS_0); - si_emit_shader_pointer(sctx, descs, - R_00B230_SPI_SHADER_USER_DATA_GS_0); si_emit_shader_pointer(sctx, descs, R_00B330_SPI_SHADER_USER_DATA_ES_0); - si_emit_shader_pointer(sctx, descs, - R_00B430_SPI_SHADER_USER_DATA_HS_0); + + /* GFX9 merged LS-HS and ES-GS. Only set RW_BUFFERS for ES and LS. */ + if (sctx->b.chip_class >= GFX9) { + si_emit_shader_pointer(sctx, descs, + R_00B430_SPI_SHADER_USER_DATA_LS_0); + } else { + si_emit_shader_pointer(sctx, descs, + R_00B230_SPI_SHADER_USER_DATA_GS_0); + si_emit_shader_pointer(sctx, descs, + R_00B430_SPI_SHADER_USER_DATA_HS_0); + } } mask = sctx->shader_pointers_dirty & @@ -2007,8 +2020,18 @@ void si_init_all_descriptors(struct si_context *sctx) /* Set default and immutable mappings. */ si_set_user_data_base(sctx, PIPE_SHADER_VERTEX, R_00B130_SPI_SHADER_USER_DATA_VS_0); - si_set_user_data_base(sctx, PIPE_SHADER_TESS_CTRL, R_00B430_SPI_SHADER_USER_DATA_HS_0); - si_set_user_data_base(sctx, PIPE_SHADER_GEOMETRY, R_00B230_SPI_SHADER_USER_DATA_GS_0); + + if (sctx->b.chip_class >= GFX9) { + si_set_user_data_base(sctx, PIPE_SHADER_TESS_CTRL, + R_00B430_SPI_SHADER_USER_DATA_LS_0); + si_set_user_data_base(sctx, PIPE_SHADER_GEOMETRY, + R_00B330_SPI_SHADER_USER_DATA_ES_0); + } else { + si_set_user_data_base(sctx, PIPE_SHADER_TESS_CTRL, + R_00B430_SPI_SHADER_USER_DATA_HS_0); + si_set_user_data_base(sctx, PIPE_SHADER_GEOMETRY, + R_00B230_SPI_SHADER_USER_DATA_GS_0); + } si_set_user_data_base(sctx, PIPE_SHADER_FRAGMENT, R_00B030_SPI_SHADER_USER_DATA_PS_0); } -- 2.30.2