From eb457a8c59cfeb602d66f1ba379b6ec3e9475d90 Mon Sep 17 00:00:00 2001 From: DJ Delorie Date: Tue, 8 Dec 2015 21:59:05 -0500 Subject: [PATCH] rx.opt (-mjsr): Add. * config/rx/rx.opt (-mjsr): Add. * config/rx/predicates.md (rx_call_operand): Avoid overflowing calls when -mjsr. * config/rx/rx.c (rx_function_ok_for_sibcall): Likewise for overflowing jumps. * doc/invoke.texi (-mjsr): Document it. From-SVN: r231439 --- gcc/ChangeLog | 9 +++++++++ gcc/config/rx/predicates.md | 4 +++- gcc/config/rx/rx.c | 3 +++ gcc/config/rx/rx.opt | 6 ++++++ gcc/doc/invoke.texi | 10 ++++++++++ 5 files changed, 31 insertions(+), 1 deletion(-) diff --git a/gcc/ChangeLog b/gcc/ChangeLog index 44eddde4b11..cc95209eba9 100644 --- a/gcc/ChangeLog +++ b/gcc/ChangeLog @@ -1,3 +1,12 @@ +2015-12-08 DJ Delorie + + * config/rx/rx.opt (-mjsr): Add. + * config/rx/predicates.md (rx_call_operand): Avoid overflowing + calls when -mjsr. + * config/rx/rx.c (rx_function_ok_for_sibcall): Likewise for + overflowing jumps. + * doc/invoke.texi (-mjsr): Document it. + 2015-12-08 Jan Hubicka PR ipa/61886 diff --git a/gcc/config/rx/predicates.md b/gcc/config/rx/predicates.md index 967a3abbec6..26667cfda05 100644 --- a/gcc/config/rx/predicates.md +++ b/gcc/config/rx/predicates.md @@ -24,7 +24,9 @@ ;; Only registers and symbol refs are allowed. (define_predicate "rx_call_operand" - (match_code "symbol_ref,reg") + (ior (match_code "reg") + (and (match_test "!TARGET_JSR") + (match_code "symbol_ref"))) ) ;; For sibcall operations we can only use a symbolic address. diff --git a/gcc/config/rx/rx.c b/gcc/config/rx/rx.c index c2c95917907..781b6b1b2b1 100644 --- a/gcc/config/rx/rx.c +++ b/gcc/config/rx/rx.c @@ -2857,6 +2857,9 @@ rx_warn_func_return (tree decl) static bool rx_function_ok_for_sibcall (tree decl, tree exp ATTRIBUTE_UNUSED) { + if (TARGET_JSR) + return false; + /* Do not allow indirect tailcalls. The sibcall patterns do not support them. */ if (decl == NULL) diff --git a/gcc/config/rx/rx.opt b/gcc/config/rx/rx.opt index 11113e2e305..56e8adf3f5c 100644 --- a/gcc/config/rx/rx.opt +++ b/gcc/config/rx/rx.opt @@ -149,3 +149,9 @@ Enable the use of the LRA register allocator. mallow-string-insns Target Report Var(rx_allow_string_insns) Init(1) Enables or disables the use of the SMOVF, SMOVB, SMOVU, SUNTIL, SWHILE and RMPA instructions. Enabled by default. + +;--------------------------------------------------- + +mjsr +Target Report Mask(JSR) +Always use JSR, never BSR, for calls. diff --git a/gcc/doc/invoke.texi b/gcc/doc/invoke.texi index 5ab565c71f8..6162a609604 100644 --- a/gcc/doc/invoke.texi +++ b/gcc/doc/invoke.texi @@ -968,6 +968,7 @@ See RS/6000 and PowerPC Options. -mint-register=@gol -mpid@gol -mallow-string-insns -mno-allow-string-insns@gol +-mjsr@gol -mno-warn-multiple-fast-interrupts@gol -msave-acc-in-interrupts} @@ -20685,6 +20686,15 @@ accesses I/O space. When the instructions are enabled GCC defines the C preprocessor symbol @code{__RX_ALLOW_STRING_INSNS__}, otherwise it defines the symbol @code{__RX_DISALLOW_STRING_INSNS__}. + +@item -mjsr +@itemx -mno-jsr +@opindex mjsr +@opindex mno-jsr +Use only (or not only) @code{JSR} instructions to access functions. +This option can be used when code size exceeds the range of @code{BSR} +instructions. Note that @option{-mno-jsr} does not mean to not use +@code{JSR} but instead means that any type of branch may be used. @end table @emph{Note:} The generic GCC command-line option @option{-ffixed-@var{reg}} -- 2.30.2