From eb6b0cf45d7588eb147d90ce790254309a69613e Mon Sep 17 00:00:00 2001 From: "Maciej W. Rozycki" Date: Sun, 24 Jan 2016 00:55:13 +0000 Subject: [PATCH] MIPS/BFD: Simplify register index calculation in BZ16_REG_FIELD Just mask higher bits off, which returns the same set of 3-bit register encodings of { 0, 1, 2, 3, 4, 5, 6, 7 } for the allowed 5-bit encodings of { 16, 17, 2, 3, 4, 5, 6, 7 }. Input has already been validated with OP16_VALID_REG. bfd/ * elfxx-mips.c (BZ16_REG_FIELD): Simplify calculation. --- bfd/ChangeLog | 4 ++++ bfd/elfxx-mips.c | 3 +-- 2 files changed, 5 insertions(+), 2 deletions(-) diff --git a/bfd/ChangeLog b/bfd/ChangeLog index 2e4f3b3c8cf..abf583be18b 100644 --- a/bfd/ChangeLog +++ b/bfd/ChangeLog @@ -1,3 +1,7 @@ +2016-01-24 Maciej W. Rozycki + + * elfxx-mips.c (BZ16_REG_FIELD): Simplify calculation. + 2016-01-24 Maciej W. Rozycki * elfxx-mips.c (BZ16_REG): Correct calculation. diff --git a/bfd/elfxx-mips.c b/bfd/elfxx-mips.c index 176970a82c3..fa14e8dd343 100644 --- a/bfd/elfxx-mips.c +++ b/bfd/elfxx-mips.c @@ -13111,8 +13111,7 @@ static const struct opcode_descriptor bz_insns_16[] = { /* Switch between a 5-bit register index and its 3-bit shorthand. */ #define BZ16_REG(opcode) ((((((opcode) >> 7) & 7) + 0x1e) & 0xf) + 2) -#define BZ16_REG_FIELD(r) \ - (((2 <= (r) && (r) <= 7) ? (r) : ((r) - 16)) << 7) +#define BZ16_REG_FIELD(r) (((r) & 7) << 7) /* 32-bit instructions with a delay slot. */ -- 2.30.2