From eb6d66e0ae163d1bb4e5f4c2e65f785e21abc9f1 Mon Sep 17 00:00:00 2001 From: lkcl Date: Fri, 6 May 2022 10:29:58 +0100 Subject: [PATCH] --- openpower/sv/SimpleV_rationale.mdwn | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) diff --git a/openpower/sv/SimpleV_rationale.mdwn b/openpower/sv/SimpleV_rationale.mdwn index 2b47344fc..e6b4e4aa5 100644 --- a/openpower/sv/SimpleV_rationale.mdwn +++ b/openpower/sv/SimpleV_rationale.mdwn @@ -254,7 +254,9 @@ gives the base concept, but in 1994 it was Peter Hsu, the designer of the MIPS R8000, who first came up with the idea of Vector-augmented prefixing of an existing Scalar ISA. Relying on a multi-issue Out-of-Order Execution Engine, the prefix would mark which of the registers were to be treated as -Scalar and which as Vector, then perform a `REP`-like loop that +Scalar and which as Vector, then, treating the Scalar "suffix" instruction +as a guide and making "scalar instruction" synonymous with "Vector element", +perform a `REP`-like loop that jammed multiple scalar operations into the Multi-Issue Execution Engine. The only reason that the team did not take this forward into a commercial product -- 2.30.2